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| tinypower tm a/d flash type 8-bit mcu with lcd & eeprom ht67f30/ht67f40/HT67F50/ht67f60 revision: v1.50 date: march 06 , 2012
rev. 1.50 2 march 06 , 2012 rev. 1.50 3 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro table of contents eates cpu features ......................................................................................................................... 7 peripheral features ................................................................................................................. 7 general description .......................................................................................... 8 selection table .................................................................................................. 9 block diagram ................................................................................................. 10 pin assignment ............................................................................................... 10 absolute maximum ratings ........................................................................... 22 d.c. characteristics ........................................................................................ 22 a.c. characteristics ........................................................................................ 27 adc characteristics ....................................................................................... 28 comparator electrical characteristics ......................................................... 29 power-on reset characteristics .................................................................... 29 lcd d.c. characteristics .............................................................................. 30 system architecture ....................................................................................... 31 clocking and pipelining ......................................................................................................... 31 program counter ................................................................................................................... 32 stack ..................................................................................................................................... 33 arithmetic and logic unit C alu ........................................................................................... 33 flash program memory .................................................................................. 34 structure ................................................................................................................................ 34 special vectors ..................................................................................................................... 34 look-up table ........................................................................................................................ 35 table program example ........................................................................................................ 35 in circuit programming ......................................................................................................... 35 ram data memory ................................................................................................................ 37 structure ................................................................................................................................ 37 special function register description ......................................................... 43 indirect addressing registers C iar0, iar1 ......................................................................... 43 memory pointers C mp0, mp1 .............................................................................................. 43 bank pointer C bp ................................................................................................................. 44 accumulator C acc ............................................................................................................... 45 program counter low register C pcl .................................................................................. 45 look-up table registers C tblp, tbhp, tblh ..................................................................... 46 status register C status .................................................................................................... 46 eeprom data memory ........................................................................................................ 48 eeprom data memory structure ........................................................................................ 48 eeprom registers .............................................................................................................. 48 reading data from the eeprom ......................................................................................... 51 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 2 march 06 , 2012 rev. 1.50 3 march 06 , 2012 writing data to the eeprom ................................................................................................ 51 write protection ..................................................................................................................... 51 eeprom interrupt ................................................................................................................ 51 programming considerations ................................................................................................ 52 oscillator ......................................................................................................... 53 oscillator overview ............................................................................................................... 53 system clock confgurations ................................................................................................ 53 external crystal/ ceramic oscillator C hxt .......................................................................... 54 external rc oscillator C erc ............................................................................................... 55 internal rc oscillator C hirc ............................................................................................... 56 external 32.768khz crystal oscillator C lxt ........................................................................ 56 lxt oscillator low power function ...................................................................................... 57 internal 32khz oscillator C lirc ........................................................................................... 57 external clock C ec .............................................................................................................. 57 supplementary oscillators .................................................................................................... 57 operating modes and system clocks .......................................................... 58 system clocks ...................................................................................................................... 58 system operation modes ...................................................................................................... 60 control register .................................................................................................................... 61 fast wake-up ........................................................................................................................ 62 operating mode switching and wake-up .............................................................................. 64 normal mode to slow mode switching ........................................................................... 64 slow mode to normal mode switching ........................................................................... 66 entering the sleep0 mode .................................................................................................. 66 entering the sleep1 mode .................................................................................................. 66 entering the idle0 mode ...................................................................................................... 67 entering the idle1 mode ...................................................................................................... 67 standby current considerations ........................................................................................... 67 wake-up ................................................................................................................................ 68 programming considerations ................................................................................................ 68 watchdog timer .............................................................................................. 69 watchdog timer clock source .............................................................................................. 69 watchdog timer control register ......................................................................................... 69 watchdog timer operation ................................................................................................... 70 reset and initialisation .......................................................................................................... 71 reset functions .................................................................................................................... 71 reset initial conditions ......................................................................................................... 74 input/output ports .......................................................................................... 85 pull-high resistors ................................................................................................................ 88 port a wake-up ..................................................................................................................... 90 i/o port control registers ..................................................................................................... 90 pin-remapping functions ...................................................................................................... 92 pin-remapping registers ....................................................................................................... 92 i/o pin structures .................................................................................................................. 98 rev. 1.50 4 march 06 , 2012 rev. 1.50 5 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro programming considerations ................................................................................................ 98 timer modules C tm ....................................................................................... 99 introduction ........................................................................................................................... 99 tm operation ...................................................................................................................... 100 tm clock source ................................................................................................................. 100 tm interrupts ....................................................................................................................... 100 tm external pins ................................................................................................................. 100 tm input/output pin control registers ............................................................................... 101 programming considerations .............................................................................................. 109 compact type tm ................................................................................................................ 110 compact tm operation ........................................................................................................ 110 compact type tm register description ............................................................................... 111 compact type tm operating modes ................................................................................... 114 compare match output mode .............................................................................................. 114 timer/counter mode ............................................................................................................ 115 pwm output mode ............................................................................................................... 116 standard type tm C stm ............................................................................. 118 standard tm operation ........................................................................................................ 118 standard type tm register description .............................................................................. 119 standard type tm operating modes .................................................................................. 124 compare output mode ........................................................................................................ 124 timer/counter mode ........................................................................................................... 126 pwm output mode .............................................................................................................. 126 single pulse mode .............................................................................................................. 128 capture input mode ............................................................................................................ 129 enhanced type tm C etm ............................................................................ 131 enhanced tm operation ..................................................................................................... 131 enhanced type tm register description ............................................................................ 132 enhanced type tm operating modes ................................................................................. 137 compare output mode ........................................................................................................ 138 timer/counter mode ........................................................................................................... 140 pwm output mode .............................................................................................................. 140 single pulse mode .............................................................................................................. 144 capture input mode ............................................................................................................ 146 analog to digital converter ......................................................................... 148 a/d overview ...................................................................................................................... 148 a/d converter register description .................................................................................... 148 a/d converter data registers C adrl, adrh ................................................................... 149 a/d converter control registers C adcr0, adcr1, acerl, acerh .............................. 149 a/d operation ..................................................................................................................... 154 a/d input pins ..................................................................................................................... 155 summary of a/d conversion steps ..................................................................................... 156 programming considerations .............................................................................................. 157 a/d transfer function ......................................................................................................... 157 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 4 march 06 , 2012 rev. 1.50 5 march 06 , 2012 a/d programming example ................................................................................................. 157 comparators ................................................................................................. 159 comparator operation ........................................................................................................ 159 comparator registers ......................................................................................................... 159 comparator interrupt ........................................................................................................... 159 programming considerations .............................................................................................. 160 serial interface module C sim ...................................................................... 162 spi interface ....................................................................................................................... 162 spi registers ...................................................................................................................... 164 spi communication ............................................................................................................ 167 i 2 c interface ........................................................................................................................ 169 i 2 c bus communication ...................................................................................................... 175 i 2 c bus start signal ............................................................................................................. 176 slave address ..................................................................................................................... 176 i 2 c bus read/write signal .................................................................................................. 176 i 2 c bus slave address acknowledge signal ....................................................................... 176 i 2 c bus data and acknowledge signal ............................................................................... 177 serial interface C spia ....................................................................................................... 178 spia interface operation .................................................................................................... 179 spia registers .................................................................................................................... 180 spia communication ................................................................................... 182 peripheral clock output ............................................................................... 184 peripheral clock operation ................................................................................................. 184 interrupts ....................................................................................................... 185 interrupt registers ............................................................................................................... 185 interrupt operation .............................................................................................................. 193 external interrupt ................................................................................................................. 197 comparator interrupt ........................................................................................................... 197 multi-function interrupt ........................................................................................................ 197 a/d converter interrupt ....................................................................................................... 198 time base interrupts ........................................................................................................... 198 serial interface module interrupt ......................................................................................... 200 external peripheral interrupt ............................................................................................... 200 serial interface interrupt ...................................................................................................... 200 eeprom interrupt .............................................................................................................. 201 lvd interrupt ....................................................................................................................... 201 tm interrupts ....................................................................................................................... 201 interrupt wake-up function ................................................................................................. 202 programming considerations .............................................................................................. 202 power down mode and wake-up ................................................................. 203 entering the idle or sleep mode ..................................................................................... 203 standby current considerations ......................................................................................... 203 wake-up .............................................................................................................................. 203 rev. 1.50 6 march 06 , 2012 rev. 1.50 7 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro low voltage detector C lvd ........................................................................ 204 lvd register ....................................................................................................................... 204 lvd operation ..................................................................................................................... 205 lcd driver ..................................................................................................... 205 lcd memory ....................................................................................................................... 207 lcd registers ..................................................................................................................... 209 lcd reset function ............................................................................................................ 210 clock source ....................................................................................................................... 210 lcd driver output ............................................................................................................... 210 lcd voltage source and biasing ........................................................................................ 212 lcd waveform timing diagrams ....................................................................................... 213 programming considerations .............................................................................................. 220 confguration options ......................................................................................................... 221 application circuits ...................................................................................... 223 instruction set ............................................................................................... 224 introduction ......................................................................................................................... 224 instruction timing ................................................................................................................ 224 moving and transferring data ............................................................................................. 224 arithmetic operations .......................................................................................................... 224 logical and rotate operations ............................................................................................ 224 branches and control transfer ........................................................................................... 225 bit operations ..................................................................................................................... 225 table read operations ....................................................................................................... 225 other operations ................................................................................................................. 225 instruction set summary ............................................................................. 226 table conventions ............................................................................................................... 226 instruction defnition .................................................................................... 228 package information .................................................................................... 238 48-pin lqfp (7mmx7mm) outline dimensions .................................................................. 238 64-pin lqfp (7mmx7mm) outline dimensions .................................................................. 239 80-pin lqfp (10mmx10mm) outline dimensions .............................................................. 240 100-pin lqfp (14mmx14mm) outline dimensions ............................................................ 241 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 6 march 06 , 2012 rev. 1.50 7 march 06 , 2012 features cpu features operating voltage: f sys = 4mhz: 2.2v~5.5v f sys = 8mhz: 2.4v~5.5v f sys = 12mhz: 2.7v~5.5v f sys = 20mhz: 4.5v~5.5v up to 0.2us instruction cycle with 20mhz system clock at v dd =5v power down and wake-up functions to reduce power consumption six oscillators: external crystal - hxt external 32.768khz crystal - lxt external rc - erc external clock - ec internal rc - hirc internal 32khz rc - lirc multi-mode operation: normal, slow, idle and sleep fully integrated internal 4mhz, 8mhz and 12mhz oscillator requires no external components all instructions executed in one or two instruction cycles table read instructions 63 powerful instructions up to 12-level subroutine nesting bit manipulation instruction peripheral features flash program memory: 2kx15 ~ 12kx16 ram data memory: 128x8 ~ 640x8 eeprom memory: 64x8 ~ 256x8 watchdog timer function up to 64 bidirectional i/o lines lcd driver function multiple pin-shared external interrupts multiple timer module for time measure, input capture, compare match output, pwm output or single pulse output function serial interfaces module with dual spi and i 2 c interfaces single serial spi interface dual comparator functions dual time-base functions for generation of fxed time interrupt signals multi-channel 12-bit resolution a/d converter low voltage reset function low voltage detect function wide range of available package types rev. 1.50 8 march 06 , 2012 rev. 1.50 9 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro flash program memory can be re-programmed up to100,000 times flash program memory data retention > 10 years eeprom data memory can be re-programmed up to 1,000,000 times eeprom data memory data retention > 10 years general description the ht67fxx series of devices are flash memory a/d with lcd type 8-bit high performance risc architecture microcontrollers, designed for applications that interface directly to analog signals and which require an lcd interface. offering users the convenience of flash memory multi- programming features, these devices also include a wide range of functions and features. other memory includes an area of ram data memory as well as an area of eeprom memory for storage of non-volatile data such as serial numbers, calibration data etc. analog features include a multi-channel 12-bit a/d converter and dual comparator functions. multiple and extremely flexible timer modules provide timing, pulse generation and pwm generation functions. communication with the outside world is catered for by including fully integrated spi or i 2 c interface functions, two popular interfaces which provide designers with a means of easy communication with external peripheral hardware. protective features such as an internal watchdog timer, low voltage reset and low voltage detector coupled with excellent noise immunity and esd protection ensure that reliable operation is maintained in hostile electrical environments. a full choice of hxt, lxt, erc, hirc and lirc oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. the ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. the inclusion of fexible i/o programming features, time-base functions along with many other features ensure that the devices will fnd excellent use in applications such as electronic metering, environmental monitoring, handheld instruments, household appliances, electronically controlled tools, motor driving in addition to many others. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 8 march 06 , 2012 rev. 1.50 9 march 06 , 2012 selection table most features are common to all devices, the main feature distinguishing them are memory capacity, i/o count, tm features, stack capacity, lcd driver and package types. the following table summarises the main features of each device. part no. v dd program memory data memory data eeprom i/o ext. interrupt lcd ht67f30 2.2v~5.5v 2kx15 128x8 64x8 32 2 20x4 21x3 21x2 ht67f40 2.2v~5.5v 4kx15 256x8 128x8 44 2 32x4 33x3 33x2 HT67F50 2.2v~5.5v 8kx16 384x8 256x8 52 2 40x4 41x3 41x2 ht67f60* 2.2v~5.5v 12kx16 640x8 256x8 64 4 56x4 57x3 57x2 part no. a/d timer module interface spi stack package ht67f30 12-bitx8 10-bit ctmx1, 10-bit etmx1 spi/i 2 c, spi 4 48 lqfp ht67f40 12-bitx8 10-bit ctmx1, 10-bit etmx1, 16-bit stmx1 spi/i 2 c, spi 8 48/64 lqfp HT67F50 12-bitx8 10-bit ctmx2, 10-bit etmx1, 16-bit stmx1 spi/i 2 c, spi 8 48/64/80 lqfp ht67f60* 12-bitx12 10-bit ctmx2, 10-bit etmx1, 16-bit stmx1 spi/i 2 c, spi 12 48/64/80 lqfp 100 lqfp note: * under development, available in 2q, 2011. rev. 1.50 10 march 06 , 2012 rev. 1.50 11 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro block diagram flash/eeprom programming circuitry (icp) watchdog timer 8-bit risc mcu core reset circuit interrupt controller erc/ec/hxt oscillator 12-bit a/d converter lirc/lxt oscillator hirc oscillator stack eeprom data memory flash program memory ram data memory spi tm0 low voltage reset low voltage detect tm1 tmn comparators tb0/tb1 i/o lcd driver sim pin assignment ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 10 march 06 , 2012 rev. 1.50 11 march 06 , 2012 ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? rev. 1.50 12 march 06 , 2012 rev. 1.50 13 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ?? ?? ? ?? ? ? ? ? ?? ? ?? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 12 march 06 , 2012 rev. 1.50 13 march 06 , 2012 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? rev. 1.50 14 march 06 , 2012 rev. 1.50 15 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 14 march 06 , 2012 rev. 1.50 15 march 06 , 2012 pin description the function of each pin is listed in the following table, however the details behind how each pin is confgured is contained in other sections of the datasheet. ht67f30 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos pb0~pb5 port b pbpu st cmos pc0~pc1 port c pcpu st cmos pd0~pd7 port d pdpu st cmos pe0~pe7 port e pepu st cmos an0~an7 adc input acerl an pa0~pa7 vref adc reference input adcr1 an pb5 c0-, c1- comparator 0, 1 input cp0c cp1c prm0 an pa3, pc1 c0+, c1+ comparator 0, 1 input an pa2, pc0 c0x, c1x comparator 0, 1 output cmos pa0, pa5 or pe2, pe6 or pe3,pe7 tck0, tck1 tm0, tm1 input st pa2, pa4 or pe0,pe1 tp0_0, tp0_1 tm0 i/o tmpc0 st cmos pa0, pa7or pd0, pd1 tp1a tm1 i/o tmpc0 st cmos pa1 or pd2 tp1b_0, tp1b_1 tm1 i/o tmpc0 st cmos pc0, pc1 or pd3, pd4 int0, int1 ext. interrupt 0, 1 st pa3, pa4 or pe4,pe5 pint peripheral interrupt st pa4 pck peripheral clock output cmos pa5 sdi spi data input st pc0 sdo spi data output cmos pc1 scs spi slave select st cmos pa6 sck spi serial clock st cmos pa7 scl i 2 c clock st nmos pa7 sda i 2 c data st nmos pc0 sdia spia data input st pa2 sdoa spia data output cmos pa3 scsa spia slave select st cmos pa0 scka spia serial clock st cmos pa1 osc1 hxt/erc pin co hxt pb1 osc2 hxt pin co hxt pb2 xt1 lxt pin co lxt pb3 xt2 lxt pin co lxt pb4 res reset input co st pb0 vdd power supply * pwr avdd adc power supply * pwr vss ground ** pwr avss adc ground ** pwr vlcd lcd power supply pwr rev. 1.50 16 march 06 , 2012 rev. 1.50 17 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro pin name function op i/t o/t pin-shared mapping vmax ic maximum voltage, connect to vdd, vlcd1 or v1 pwr v1,v2,c1,c2 lcd voltage pump seg0~7 lcd segment output cmos pd0~pd7 seg8~15 lcd segment output cmos pe0~pe7 seg16~19, 24 lcd segment output cmos com0~3 lcd common output cmos note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is the device power supply while avdd is the adc power supply. the avdd pin is bonded together internally with vdd. **: vss is the device ground pin while avss is the adc ground pin. the avss pin is bonded together internally with vss. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. ht67f40 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos pb0~pb5 port b pbpu st cmos pc0~pc5 port c pcpu st cmos pd0~pd7 port d pdpu st cmos pe0~pe7 port e pepu st cmos pf0~pf7 port f pfpu st cmos an0~an7 adc input acerl an pa0~pa7 vref adc reference input adcr1 an pb5 c0-, c1- comparator 0, 1 input cp0c cp1c an pa3, pc3 c0+, c1+ comparator 0, 1 input cp0c cp1c an pa2, pc2 c0x, c1x comparator 0, 1 output cp0c cp1c prm0 cmos pa0, pa5 or pe2,pe6 or pe3, pe7 tck0~tck2 tm0~tm2 input prm1 st pa2, pa4, pc2 or pe0, pe1, pe2 tp0_0, tp0_1 tm0 i/o tmpc0 prm2 st cmos pa0, pc5 or pd0, pd1 tp1a tm1 i/o tmpc0 prm2 st cmos pa1 or pd2 tp1b_0~tp1b_2 tm1 i/o tmpc0 prm2 st cmos pc0, pc1, pc5 or pd3,pd4,pd5 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 16 march 06 , 2012 rev. 1.50 17 march 06 , 2012 pin name function op i/t o/t pin-shared mapping tp2_0, tp2_1 tm2 i/o tmpc1 prm2 st cmos pc3, pc4 or pd6, pd7 int0, int1 ext. interrupt 0, 1 prm1 st pa3, pa4 or pe4, pe5 pintb peripheral interrupt prm0 st pa4 or pc0 pck peripheral clock output prm0 cmos pa5 or pc1 sdi spi data input prm0 st pc0 or pc4 sdo spi data output prm0 cmos pc1 or pc5 scs spi slave select prm0 st cmos pa6 or pc2 sck spi serial clock prm0 st cmos pa7 or pc3 scl i 2 c clock prm0 st nmos pa7 or pc3 sda i 2 c data prm0 st nmos pc0 or pc4 sdia spia data input st pa2 sdoa spia data output cmos pa3 scsa spia slave select st cmos pa0 scka spia serial clock st cmos pa1 osc1 hxt/erc pin co hxt pb1 osc2 hxt pin co hxt pb2 xt1 lxt pin co lxt pb3 xt2 lxt pin co lxt pb4 res reset input co st pb0 vdd power supply * pwr avdd adc power supply * pwr vss ground ** pwr avss adc ground ** pwr vlcd lcd power supply pwr vmax ic maximum voltage, connect to vdd, vlcd1 or v1 pwr v1,v2,c1,c2 lcd voltage pump seg0~7 lcd segment output cmos pd0~pd7 seg8~15 lcd segment output cmos pe0~pe7 seg16~23 lcd segment output cmos pf0~pf7 seg24~32 lcd segment output cmos com0~3 lcd common output cmos note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is the device power supply while avdd is the adc power supply. the avdd pin is bonded together internally with vdd. **: vss is the device ground pin while avss is the adc ground pin. the avss pin is bonded together internally with vss. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. rev. 1.50 18 march 06 , 2012 rev. 1.50 19 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro HT67F50 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos pb0~pb7 port b pbpu st cmos pc0~pc5 port c pcpu st cmos pd0~pd7 port d pdpu st cmos pe0~pe7 port e pepu st cmos pf0~pf7 port f pfpu st cmos pg0~pg5 port g pgpu st cmos an0~an7 adc input acerl an pa0~pa7 vref adc reference input adcr1 an pb5 c0-, c1- comparator 0, 1 input cp0c cp1c an pa3, pc3 c0+, c1+ comparator 0, 1 input cp0c cp1c an pa2, pc2 c0x, c1x comparator 0, 1 output cp0c cp1c prm0 cmos pa0, pa5 or pe2,pe6 or pe3, pe7 tck0~tck3 tm0~tm3 input prm1 st pa2, pa4, pc2, pc4 or pe0, pe1, pe2, tp0_0, tp0_1 tm0 i/o tmpc0 prm2 st cmos pa0, pc5 or pd0,pd1 tp1a tm1 i/o tmpc0 prm2 st cmos pa1 or pd2 tp1b_0~tp1b_2 tm1 i/o tmpc0 prm2 st cmos pc0, pc1, pc5 or pd3, pd4, pd5 tp2_0, tp2_1 tm2 i/o tmpc1 prm2 st cmos pc3, pc4 or pd6,pd7 tp3_0, tp3_1 tm3 i/o tmpc1 prm2 st cmos pg0, pg3 or pf0,pf1 int0, int1 ext. interrupt 0, 1 prm1 st pa3, pa4 or pe4,pe5 pintb peripheral interrupt prm0 st pa4 or pc0 or pg0 pck peripheral clock output prm0 cmos pa5 or pc1 or pg1 sdi spi data input prm0 st pc0 or pc4 or pg4 sdo spi data output prm0 cmos pc1 or pc5 or pg5 scs spi slave select prm0 st cmos pa6 or pc2 or pg2 sck spi serial clock prm0 st cmos pa7 or pc3 or pg3 scl i 2 c clock prm0 st nmos pa7 or pc3 or pg3 sda i 2 c data prm0 st nmos pc0 or pc4 or pg4 sdia spia data input st pa2 sdoa spia data output cmos pa3 scsa spia slave select st cmos pa0 scka spia serial clock st cmos pa1 osc1 hxt/erc pin co hxt pb1 osc2 hxt pin co hxt pb2 xt1 lxt pin co lxt pb3 xt2 lxt pin co lxt pb4 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 18 march 06 , 2012 rev. 1.50 19 march 06 , 2012 pin name function op i/t o/t pin-shared mapping res reset input co st pb0 vdd power supply * pwr avdd adc power supply * pwr vss ground ** pwr avss adc ground ** pwr vlcd lcd power supply pwr vmax ic maximum voltage, connect to vdd, vlcd1 or v1 pwr v1,v2,c1,c2 lcd voltage pump seg0~7 lcd segment output cmos pd0~pd7 seg8~15 lcd segment output cmos pe0~pe7 seg16~23 lcd segment output cmos pf0~pf7 seg24~40 lcd segment output cmos com0~3 lcd common output cmos note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is the device power supply while avdd is the adc power supply. the avdd pin is bonded together internally with vdd. **: vss is the device ground pin while avss is the adc ground pin. the avss pin is bonded together internally with vss. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. rev. 1.50 20 march 06 , 2012 rev. 1.50 21 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ht67f60 pin name function op i/t o/t pin-shared mapping pa0~pa7 port a pawu papu st cmos pb0~pb7 port b pbpu st cmos pc0~pc7 port c pcpu st cmos pd0~pd7 port d pdpu st cmos pe0~pe7 port e pepu st cmos pf0~pf7 port f pfpu st cmos pg0~pg7 port g pgpu st cmos ph0~ph7 port h phpu st cmos an0~an11 adc input acerh an pa0~pa7, ph0~ph3 vref adc reference input adcr1 an pb5 c0-, c1- comparator 0, 1 input cp0c cp1c an pa3, pc3 c0+, c1+ comparator 0, 1 input cp0c cp1c an pa2, pc2 c0x, c1x comparator 0, 1 output cp0c cp1c prm0 cmos pa0, pa5 or pe2, pe6 or pe3, pe7 tck0~tck3 tm0~tm3 input prm1 st pa2, pa4, pc2, pc4 or pe0, pe1, pe2, ? tp0_0, tp0_1 tm0 i/o tmpc0 prm2 st cmos pa0, pc5 or pd0,pd1 tp1a tm1 i/o tmpc0 prm2 st cmos pa1 or pd2 tp1b_0~tp1b_2 tm1 i/o tmpc0 prm2 st cmos pc0, pc1, pc5 or pd3,pd4,pd5 tp2_0, tp2_1 tm2 i/o tmpc1 prm2 st cmos pc3, pc4 or pd6,pd7 tp3_0, tp3_1 tm3 i/o tmpc1 prm2 st cmos pg3, pg0 or pf0,pf1 int0~int3 ext. interrupt 0~3 prm1 st pa3, pa4, pc4, pc5 or,pe4,pe5,pe6 pintb peripheral interrupt prm0 st pa4 or pc0 or pg0 pck peripheral clock output prm0 ? cmos pa5 or pc1 or pg1 sdi spi data input prm0 st pc0 or pc4 or pg4 sdo spi data output prm0 cmos pc1 or pc5 or pg5 scs spi slave select prm0 st cmos pa6 or pc2 or pg2 sck spi serial clock prm0 st cmos pa7 or pc3 or pg3 scl i 2 c clock prm0 st nmos pa7 or pc3 or pg3 sda i 2 c data prm0 st nmos pc0 or pc4 or pg4 sdia spia data input st pa2 sdoa spia data output cmos pa3 scsa spia slave select st cmos pa0 scka spia serial clock st cmos pa1 osc1 hxt/erc pin co hxt pb1 osc2 hxt pin co hxt pb2 xt1 lxt pin co lxt pb3 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 20 march 06 , 2012 rev. 1.50 21 march 06 , 2012 pin name function op i/t o/t pin-shared mapping xt2 lxt pin co lxt pb4 res reset input co st pb0 vdd power supply * pwr avdd adc power supply * pwr vss ground ** pwr avss adc ground ** pwr vlcd lcd power supply pwr vmax ic maximum voltage, connect to vdd, vlcd1 or v1 pwr v1,v2,c1,c2 lcd voltage pump seg0~7 lcd segment output cmos pd0~pd7 seg8~15 lcd segment output cmos pe0~pe7 seg16~23 lcd segment output cmos pf0~pf7 seg24~31 lcd segment output cmos ph6~ph7, pb6~pb7, pg6~pg7, pc6~pc7 seg32~56 lcd segment output cmos com0~3 lcd common output cmos note: i/t: input type; o/t: output type op: optional by confguration option (co) or register option pwr: power; co: confguration option; st: schmitt trigger input cmos: cmos output; nmos: nmos output an: analog input pin hxt: high frequency crystal oscillator lxt: low frequency crystal oscillator *: vdd is the device power supply while avdd is the adc power supply. the avdd pin is bonded together internally with vdd. **: vss is the device ground pin while avss is the adc ground pin. the avss pin is bonded together internally with vss. as the pin description summary table applies to the package type with the most pins, not all of the above listed pins may be present on package types with smaller numbers of pins. rev. 1.50 22 march 06 , 2012 rev. 1.50 23 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro absolute maximum ratings supply voltage ................................................................................................ v ss -0.3v to v ss +6.0v input voltage .................................................................................................. v ss -0.3v to v dd +0.3v i ol total .................................................................................................... 80ma total power dissipation ........................................................................................................ 500mw storage temperature .................................................................................................. -50 c to 125c operating temperature ................................................................................................ -40 c to 85 c i oh total .................................................................................................. -80ma note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specifcation is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage (hxt, erc, hirc) f sys =4mhz 2.2 5.5 v f sys =8mhz 2.4 5.5 v f sys =12mhz 2.7 5.5 v f sys =20mhz 4.5 5.5 v i dd1 operating current (crystal osc, f sys =f h , f s =f sub =f lxt or f lirc ) 3v no load, f h =455khz, adc off, wdt enable 100 150 a 5v 300 450 a 3v no load, f h =1mhz, adc off, wdt enable 240 360 a 5v 480 720 a 3v no load, f h =4mhz, adc off, wdt enable 400 600 a 5v 0.8 1.2 ma 3v no load, f h =8mhz, adc off, wdt enable 0.8 1.2 ma 5v 1.6 2.4 ma 3v no load, f h =12mhz, adc off, wdt enable 1.2 1.8 ma 5v 2.4 3.6 ma 3v no load, f h =16mhz, adc off, wdt enable 1.6 2.4 ma 5v 3.2 4.8 ma 5v no load, f h =20mhz, adc off, wdt enable 4.0 6.0 ma i dd2 operating current (erc osc, f sys =f h , f s =f sub =f lxt or f lirc ) 3v no load, f h =455khz, adc off, wdt enable 120 180 a 5v 240 360 a 3v no load, f h =1mhz, adc off, wdt enable 200 300 a 5v 400 600 a 3v no load, f h =4mhz, adc off, wdt enable 500 750 a 5v 1 1.5 ma 3v no load, f h =8mhz, adc off, wdt enable 1 1.5 ma 5v 2 3.0 ma 3v no load, f h =12mhz, adc off, wdt enable 1.5 2.75 ma 5v 3.0 4.5 ma 5v no load, f h =16mhz, adc off, wdt enable 4.0 6.0 a i dd3 operating current (hirc osc, f sys =f h , f s =f sub =f lxt or f lirc ) 3v no load, f h =4mhz, adc off, wdt enable 400 600 a 5v 0.8 1.2 ma 3v no load, f h =8mhz, adc off, wdt enable 0.8 1.2 ma 5v 1.6 2.4 ma 3v no load, f h =12mhz, adc off, wdt enable 1.2 1.8 ma 5v 2.4 3.6 ma ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 22 march 06 , 2012 rev. 1.50 23 march 06 , 2012 symbol parameter test conditions min. typ. max. unit v dd conditions i dd4 operating current (ec mode, f sys =f h , f s =f sub =f lxt or f lirc ) 3v no load, f h =4mhz, adc off, wdt enable 360 480 a 5v 720 1080 a i dd5 operating current (crystal osc, f sys =f l , f s =f sub =f lxt or f lirc ) 3v no load, f h =8mhz, f l =f h /2, adc off, wdt enable 500 750 a 5v 1 1.5 ma 3v no load, f h =8mhz, f l =f h /4, adc off, wdt enable 350 525 a 5v 0.7 1.05 ma 3v no load, f h =8mhz, f l =f h /8, adc off, wdt enable 300 450 a 5v 600 900 a 3v no load, f h =8mhz, f l =f h /16, adc off, wdt enable 280 420 a 5v 560 840 a 3v no load, f h =8mhz, f l =f h /32, adc off, wdt enable 250 375 a 5v 500 750 a 3v no load, f h =8mhz, f l =f h /64, adc off, wdt enable 230 345 a 5v 440 660 a i dd6 operating current (crystal osc, f sys =f l , f s =f sub =f lxt or f lirc ) 3v no load, f h =4mhz, f l =f h /2, adc off, wdt enable 300 600 a 5v no load, f h =4mhz, f l =f h /2, adc off, wdt enable 600 900 a 3v no load, f h =4mhz, f l =f h /4, adc off, wdt enable 200 300 a 5v no load, f h =4mhz, f l =f h /4, adc off, wdt enable 400 600 a i dd7 operating current (crystal osc, f sys =f l , f s =f sub =f lxt or f lirc ) 3v no load, f h =12mhz, f l =f h /2, adc off, wdt enable 0.8 1.2 ma 5v no load, f h =12mhz, f l =f h /2, adc off, wdt enable 1.6 2.4 ma 3v no load, f h =12mhz, f l =f h /4, adc off, wdt enable 0.5 0.75 ma 5v no load, f h =12mhz, f l =f h /4, adc off, wdt enable 1 1.5 ma i dd8 operating current (rtc osc, f sys =f l =f lxt , f s =f sub =f lxt ) (except HT67F50, ht67f60) 3v no load, adc off, wdt enable, qosc=0 10 15 a 5v 20 30 a 3v no load, adc off, wdt enable, qosc=1 10 15 a 5v 20 30 a i dd8a operating current (rtc osc, f sys =f l =f lxt , f s =f sub =f lxt ) (HT67F50, ht67f60) 3v no load, adc off, wdt enable, qosc=0 20 30 a 5v 40 60 a 3v no load, adc off, wdt enable, qosc=1 20 30 a 5v 40 60 a i dd9 operating current (lirc osc, f sys =f l =f lirc , f s =f sub =f lirc ) (except HT67F50, ht67f60) 3v no load, adc off, wdt enable 10 15 a 5v 20 30 a rev. 1.50 24 march 06 , 2012 rev. 1.50 25 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro symbol parameter test conditions min. typ. max. unit v dd conditions i dd9a operating current (lirc osc, f sys =f l =f lirc , f s =f sub =f lirc ) (HT67F50, ht67f60) 3v no load, adc off, wdt enable 20 30 a 5v 40 60 a i dd10 operating current (rtc+lirc osc, f sys =f l =f lxt , f s =f sub =f lirc ) (except HT67F50, ht67f60) 3v no load, adc off, wdt enable, qosc=0 10 15 a 5v 20 30 a i dd10a operating current (rtc+lirc osc, f sys =f l =f lxt , f s =f sub =f lirc ) (HT67F50, ht67f60) 3v no load, adc off, wdt enable, qosc=0 15 30 a i stb1 stanby current (idle) (crystal osc, f sys =f h , f s =f sub =f lxt or f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =8mhz, spi or i 2 c on, pck on, pck=f sys /8 0.3 0.5 ma 5v 0.5 0.8 ma i stb2 stanby current (idle) (crystal osc, f sys =off, f s =t1) 3v no load, system halt, adc off, wdt enable, f sys =8mhz 1.5 3.0 a 5v 2.5 5.0 a i stb3 stanby current (idle) (crystal osc, f sys =off, f s =f sub =f lxt or f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =8mhz 1.5 3.0 a 5v 2.5 5.0 a i stb4 stanby current (idle) (erc osc, f sys =off, f s =f sub =f lxt ) 3v no load, system halt, adc off, wdt enable, f sys =8mhz 1.5 3.0 a 5v 2.5 5.0 a i stb5 stanby current (idle) (hirc osc, f sys =off, f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =8mhz 1.5 3.0 a 5v 2.5 5.0 a i stb7 stanby current (idle) (crystal osc, f sys =off, f s =f sub =f lxt or f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =8mhz/64 1.5 3.0 a 5v 2.5 5.0 a i stb8 stanby current (idle) (rtc osc, f sys =f l =f lxt , f s =f sub =f lxt ) 3v no load, system halt, adc off, wdt enable, f sys =32768hz 1.9 4.0 a 5v 3.3 7.0 a i stb9 stanby current (idle) (rtc osc, f sys =off, f s =t1) 3v no load, system halt, adc off, wdt enable, f sys =32768hz 1.5 3.0 a 5v 2.5 5.0 a ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 24 march 06 , 2012 rev. 1.50 25 march 06 , 2012 symbol parameter test conditions min. typ. max. unit v dd conditions i stb10 stanby current (idle) (rtc osc, f sys =off, f s =f sub =f lxt ) 3v no load, system halt, adc off, wdt enable, f sys =32768hz 1.5 3.0 a 5v 2.5 5.0 a i stb11 stanby current (idle) (lirc osc, f sys =off, f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =32khz 1.5 3.0 a 5v 2.5 5.0 a i stb12 stanby current (idle) (rtc osc, f sys =off, f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =32768hz 1.5 3.0 a 5v 2.5 5.0 a i stb13 stanby current (sleep) (crystal osc, f sys =off, f s =f sub =f lxt or f lirc ) 3v no load, system halt, adc off, wdt disable, f sys =12mhz 0.1 1 a 5v 0.3 2 a i stb14 stanby current (sleep) (crystal osc, f sys =off, f s =f sub =f lxt ) 3v no load, system halt, adc off, wdt enable, f sys =12mhz 1.5 3.0 a 5v 2.5 5.0 a i stb15 stanby current (sleep) (crystal osc, f sys =off, f s =f sub =f lirc ) 3v no load, system halt, adc off, wdt enable, f sys =12mhz 1.5 3.0 a 5v 2.5 5.0 a i stb16 stanby current (sleep) (rtc osc, f sys =off, f s =f sub =f lxt or f lirc ) 3v no load, system halt, adc off, wdt disable, f sys =32768hz 0.1 1 a 5v 0.3 2 a i stb17 stanby current (sleep) (rtc osc, f sys =off, f s =f sub =f lxt ) 3v no load, system halt, adc off, wdt enable, f sys =32768hz 1.5 3.0 a 5v 2.5 5.0 a i stb18 stanby current (sleep) (crystal osc, f sys =off, f s =f sub =f lxt or f lirc ) no load, system halt, adc off, wdt disable, f sys =12mhzhz, lvr enable and lvden=1 20 30 a v il1 input low voltage for i/o ports, tmr and intb 0 0.3v dd v v ih1 input high voltage for i/o ports, tmr and intb 0.7v dd v dd v v il2 input low voltage ( res ) 0 0.4v dd v v ih2 input high voltage ( res ) 0.9v dd v dd v rev. 1.50 26 march 06 , 2012 rev. 1.50 27 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro symbol parameter test conditions min. typ. max. unit v dd conditions v lvr1 low voltage reset voltage lvr enable, 2.1v option -5% typ. 2.1 +5% typ. v v lvr2 lvr enable, 2.55v option 2.55 v v lvr3 lvr enable, 3.15v option 3.15 v v lvr4 lvr enable, 4.2v option 4.2 v i lvr low voltage reset current lvr enable, lvden=0 20 30 a v lvd1 low voltage detector voltage lvden = 1, v lvd = 2.0v -5% typ. 2.0 +5% typ. v v lvd2 lvden = 1, v lvd = 2.2v 2.2 v v lvd3 lvden = 1, v lvd = 2.4v 2.4 v v lvd4 lvden = 1, v lvd = 2.7v 2.7 v v lvd5 lvden = 1, v lvd = 3.0v 3.0 v v lvd6 lvden = 1, v lvd = 3.3v 3.3 v v lvd7 lvden = 1, v lvd = 3.6v 3.6 v v lvd8 lvden = 1, v lvd = 4.4v 4.4 v i lvd1 low voltage detector current lvr disable, lvden = 1 20 30 a i lvd2 lvr enable, lvden = 1 30 45 a i ol i/o port sink current 3v v ol =0.1v dd 4 8 ma 5v v ol =0.1v dd 10 20 ma i oh i/o port, source current 3v v oh =0.9v dd -2 -4 ma 5v v oh =0.9v dd -5 -10 ma r ph pull-high resistance of i/o ports 3v 20 60 100 k 5v 10 30 50 k av dd analog operating voltage v ref =av dd 2.7 5.5 v v bg bandgap reference with buffer voltage -3% typ. 1.19 +3% typ. v i bg bandgap reference with buffer driving current v bg is used, lvr disable, lvden=0 (opa enable d ) 200 400 a ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 26 march 06 , 2012 rev. 1.50 27 march 06 , 2012 a.c. characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions f cpu operating clock 2.2~5.5v dc 4 mhz 2.4~5.5v dc 8 mhz 2.7~5.5v dc 12 mhz 4.5~5.5v dc 20 mhz f sys system clock (hxt) 2.2~5.5v 0.4 4 mhz 2.2~5.5v 0.4 8 mhz 2.7~5.5v 0.4 12 mhz 4.5~5.5v 0.4 20 mhz f hirc system clock (hirc) 3v/5v ta=25c -2% 4 +2% mhz 3v/5v ta=25c -2% 8 +2% mhz 5v ta=25c -2% 12 +2% mhz 3v/5v ta=0~70c -5% 4 +5% mhz 3v/5v ta=0~70c -5% 8 +5% mhz 5v ta=0~70c -5% 12 +5% mhz 2.2v~3.6v ta=0~70c -10% 4 +10% mhz 3.0v~5.5v ta=0~70c -10% 4 +10% mhz 2.4v~3.6v ta=0~70c -7% 8 +7% mhz 3.0v~5.5v ta=0~70c -7% 8 +7% mhz 3.0v~5.5v ta=0~70c -7% 12 +7% mhz 2.2v~3.6v ta=-40~85c -10% 4 +10% mhz 3.0v~5.5v ta=-40~85c -10% 4 +10% mhz 2.4v~3.6v ta=-40~85c -10% 8 +10% mhz 3.0v~5.5v ta=-40~85c -10% 8 +10% mhz 3.0v~5.5v ta=-40~85c -10% 12 +10% mhz f erc system clock (erc) 5v ta = 25 c external r erc = 150 k -2% 4 +2% mhz 5v ta = 0~70 c external r erc = 150 k -5% 4 +5% mhz 5v ta = -40~85 c external r erc = 150 k -7% 4 +7% mhz 3.0v~5.5v ta = -40~85 c external r erc = 150 k -9% 4 +9% mhz 2.2v~5.5v ta = -40~85 c external r erc = 150 k -12% 4 +12% mhz f sys4 system clock (32768 crystal) 32768 hz t res external reset low pulse width 1 s t sst system start- up timer period (wake-up from halt) f sys =xtal or rtc osc 1024 1025 t sys f sys =erc or hirc osc 15 17 f sys =lirc osc 1 3 rev. 1.50 28 march 06 , 2012 rev. 1.50 29 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro symbol parameter test conditions min. typ. max. unit v dd conditions t int interrupt pulse width 1 t sys t lvr low voltage width to reset 120 240 480 s t lvd low voltage width to interrupt 20 45 90 s t lvds lvdo stable time for all v lvd , lvr disable 15 s for v lvd disable, lvr enable 25 s t bgs vbg turn on stable time 10 ms t ad a/d clock period 2.7~5.5v 0.5 100 s t adc ad conversion time (note2) 2.7~5.5v 12 bit adc 16 t ad t on2st (#) adc on to adc start 2.7~5.5v 2 s t eerd eeprom read time 1 2 4 t sys t eewr eeprom write timet 1 2 4 ms adc characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions av dd adc operating voltage 2.7 5.5 v v adi ad input voltage 0 v ref v v ref adc reference voltage 2 av dd v dnl differential non-linearity 5v t ad = 1.0s 1 2 lsb inl integral non-linearity 5v t ad = 1.0s 2 4 lsb i adc additional power consumption if a/d converter is used 3v no load, t ad = 0.5s 0.90 1.35 ma 5v no load, t ad = 0.5s 1.20 1.80 ma t adck a/d clock period 0.5 10 s t adc a/d conversion time (include a/d sample and hold time) 12-bit adc 16 t adck t sh a/d sampling time ? 4 t adck note: 1. t sys= 1/f sys 2. * for f erc dvwkhuhvlvwruwrohudqfhzloolqxhqfhwkhiuhtxhqfdsuhflvlrquhvlvwrulvuhfrpphqghg 7rpdlqwdlqwkhdffxudfriwkhlqwhuqdo+,5rvfloodwruiuhtxhqfdghfrxsolqjfdsdflwruvkrxogeh connected between vdd and vss and located as close to the device as possible. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 28 march 06 , 2012 rev. 1.50 29 march 06 , 2012 comparator electrical characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v cmp comparator operating voltage 2.2 5.5 v i cmp comparator operating current 3v 37 56 a 5v 130 200 a v cmpos comparator input offset voltage 10 10 mv v hys hysteresis width 20 40 60 mv v cm comparator common mode voltage range v ss v dd -1.4v v a ol comparator open loop gain 60 80 db t pd comparator response time with 100mv overdrive (note) 200 400 ns note: measured with comparator one input pin at v cm = (v dd -1.4)/2 while the other pin input transition from v ss to (v cm +100mv) or from v dd to (v cm -100mv). power-on reset characteristics ta=25c symbol parameter test conditions min. typ. max. unit v dd conditions v por v dd start voltage to ensure power-on reset 100 mv rr vdd v dd raising rate to ensure power-on reset 0.035 v/ms t por minimum time for v dd stays at v por to ensure power-on reset 1 ms rev. 1.50 30 march 06 , 2012 rev. 1.50 31 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro lcd d.c. characteristics ta=25c symbol parameter v dd condition min. typ. max. unit i stb1 standby current (idle) (f sys , f wdt off, fs= f sub = 32768 or 32k rc osc) 3 no load, system halt, lcd on, wdt off, c type v lcd =v dd , 1/2 bias, 6 10 a 5 10 15 a i stb2 standby current (idle) (f sys , f wdt off, fs= f sub = 32768 or 32k rc osc) 3 no load, system halt, lcd on, wdt off, c type v lcd = v dd , 1/3 bias, 6 10 a 5 10 15 a i stb3 standby current (idle) (f sys , f wdt off, fs= f sub = 32768 or 32k rc osc) 3 no load, system halt, lcd on, wdt off, r type v lcd =v d d, 1/2 bias(i bias =7.5a) 13.5 20 a 5 22.5 40 a i stb4 standby current (idle) (f sys , f wdt off, fs= f sub = 32768 or 32k rc osc) 3 no load, system halt, lcd on, wdt off, r type v lcd =v dd , 1/2 bias(i bias =15a) 21 40 a 5 35 60 a i stb5 standby current (idle) (f sys , f wdt off, fs= f sub = 32768 or 32k rc osc) 3 no load, system halt, lcd on, wdt off, r type v lcd =v dd , 1/2 bias(i bias =45a) 51 80 a 5 85 160 a i stb6 standby current (idle) (f sys , f wdt off, *fs= f sub = % 32768 or 32k rc osc) 3 no load, system halt, lcd on, wdt off, r type v lcd =v dd , 1/2 bias(i bias =90a) 96 160 a 5 160 320 a i stb7 standby current (idle) (f sys , f wdt off, fs= f sub = 32768 or 32k rc osc) 3 no load, system halt, lcd on, wdt off, r type v lcd =v dd , 1/3 bias(i bias =7.5a) 11 20 a 5 18.3 40 a i stb8 standby current (idle) (f sys , f wdt off, fs= f sub = 32768 or 32k rc osc) 3 no load, system halt, lcd on, wdt off, r type v lcd =v dd , 1/3 bias(i bias =15a) 16 25 a 5 26.6 50 a i stb9 standby current (idle) (f sys , f wdt off, fs= f sub = 32768 or 32k rc osc) 3 no load, system halt, lcd on, wdt off, r type v lcd =v dd , 1/3 bias(i bias =45a) 36 50 a 5 60 100 a i stb10 standby current (idle) (f sys , f wdt off, fs= f sub =32768 or 32k rc osc) 3 no load, system halt, lcd on, wdt off, r type v lcd =v dd , 1/3 bias(i bias =90a) 66 100 a 5 110 200 a i ol2 lcd common and segment sink current 3 v ol =0.1v lcd 210 420 a 5 350 700 a i oh2 lcd common and segment source current 3 v oh =0.9v lcd -80 -160 a 5 -180 -360 a ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 30 march 06 , 2012 rev. 1.50 31 march 06 , 2012 system architecture a key factor in the high-performance features of the holtek range of microcontrollers is attributed to their internal system architecture. the range of devices take advantage of the usual features found within risc microcontrollers providing increased speed of operation and enhanced performance. the pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. an 8-bit wide alu is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. the internal data path is simplifed by moving data through the accumulator and the alu. certain internal registers are implemented in the data memory and can be directly or indirectly addressed. the simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional i/o and a/d control system with maximum reliability and flexibility. this makes the device suitable for low-cost, high-volume production for controller applications. clocking and pipelining the main system clock, derived from either a hxt, lxt, hirc, lirc, ec or erc oscillator is subdivided into four internally generated non-overlapping clocks, t1~t4. the program counter is incremented at the beginning of the t1 clock during which time a new instruction is fetched. the remaining t2~t4 clocks carry out the decoding and execution functions. in this way, one t1~t4 clock cycle forms one instruction cycle. although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. the exception to this are instructions where the contents of the program counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. for instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. an extra cycle is required as the program takes one cycle to frst obtain the actual jump or call address and then another cycle to actually execute the branch. the requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. ? ? ? ? ? ? ? ? system clocking and pipelining rev. 1.50 32 march 06 , 2012 rev. 1.50 33 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ? ? ? ? ? ? ? ? ? ? instruction fetching program counter during program execution, the program counter is used to keep track of the address of the next instruction to be executed. it is automatically incremented by one each time an instruction is executed except for instructions, such as jmp or call that demand a jump to a non- consecutive program memory address. only the lower 8 bits, known as the program counter low register, are directly addressable by the application program. when executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the program counter. for conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. device program counter program counter high byte pcl register ht67f30 pc10~pc8 pcl7~pcl0 ht67f40 pc11~pc8 HT67F50 pc12~pc8 ht67f60 pc13~pc8 program counter the lower byte of the program counter, known as the program counter low register or pcl, is available for program control and is a readable and writeable register. by transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. when such program jumps are executed it should also be noted that a dummy cycle will be inserted. manipulating the pcl register may cause program branching, so an extra cycle is needed to pre-fetch. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 32 march 06 , 2012 rev. 1.50 33 march 06 , 2012 stack this is a special part of the memory which is used to save the contents of the program counter only. the stack has multiple levels depending upon the device and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer, and is neither readable nor writeable. at a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction, ret or reti, the program counter is restored to its previous value from the stack. after a device reset, the stack pointer will point to the top of the stack. if the stack is full and an enabled interrupt takes place, the interrupt request fag will be recorded but the acknowledge signal will be inhibited. when the stack pointer is decremented, by ret or reti, the interrupt will be serviced. this feature prevents stack overfow allowing the programmer to use the structure more easily. however, when the stack is full, a call subroutine instruction can still be executed which will result in a stack overflow. precautions should be taken to avoid such cases which might cause unpredictable program branching. if the stack is overfow, the frst program counter save in the stack will be lost. device stack levels ht67f30 4 ht67f40/HT67F50 8 ht67f60 12 arithmetic and logic unit C alu the arithmetic-logic unit or alu is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. connected to the main microcontroller data bus, the alu receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specifed register. as these alu calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to refect these changes. the alu supports the following functions: arithmetic operations: add, addm, adc, adcm, sub, subm, sbc, sbcm, daa logic operations: and, or, xor, andm, orm, xorm, cpl, cpla rotation rra, rr, rrca, rrc, rla, rl, rlca, rlc increment and decrement inca, inc, deca, dec branch decision, jmp, sz, sza, snz, siz, sdz, siza, sdza, call, ret, reti rev. 1.50 34 march 06 , 2012 rev. 1.50 35 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro flash program memory the program memory is the location where the user code or program is stored. for this device series the program memory is flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modifcation on the same device. by using the appropriate programming tools, these flash devices offer users the flexibility to conveniently debug and develop their applications while also offering a means of feld programming and updating. structure the program memory has a capacity of 2kx15 bits to 12kx16 bits. the program memory is addressed by the program counter and also contains data, table information and interrupt entries. table data, which can be setup in any location within the program memory, is addressed by a separate table pointer register. device capacity banks ht67f30 2kx15 0 ht67f40 4kx15 0 HT67F50 8kx16 0 ht67f60 12kx16 0, 1 the ht67f60 has its program memory divided into two banks, bank 0 and bank 1. the required bank is selected using bit 5 of the bp register. special vectors within the program memory, certain locations are reserved for the reset and interrupts. the location 000h is reserved for use by the device reset for program initialisation. after a device reset is initiated, the program will jump to this location and begin execution. porgram memory structure ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 34 march 06 , 2012 rev. 1.50 35 march 06 , 2012 look-up table any location within the program memory can be defned as a look-up table where programmers can store fxed data. to use the look-up table, the table pointer must frst be setup by placing the address of the look up data to be retrieved in the table pointer register, tblp and tbhp. these registers defne the total address of the look-up table. after setting up the table pointer, the table data can be retrieved from the program memory using the tabrd[m] or tabrdl[m] instructions, respectively. when the instruction is executed, the lower order table byte from the program memory will be transferred to the user defined data memory register [m] as specified in the instruction. the higher order table data byte from the program memory will be transferred to the tblh special register. any unused bits in this transferred higher order byte will be read as0. the accompanying diagram illustrates the addressing data fow of the look-up table. table program example the following example shows how the table pointer and table data is defned and retrieved from the microcontroller. this example uses raw table data located in the program memory which is stored there using the org statement. the value at this org statement is 700h which refers to the start address of the last page within the 2k program memory of the ht67f30. the table pointer is setup here to have an initial value of 06h. this will ensure that the frst data read from the data table will be at the program memory address 706h or 6 locations after the start of the last page. note that the value for the table pointer is referenced to the first address of the present page if the tabrd [m] instruction is being used. the high byte of the table data which in this case is equal to zero will be transferred to the tblh register automatically when the tabrd [m] instruction is executed. because the tblh register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and interrupt service routine use table read instructions. if using the table read instructions, the interrupt service routines may change the value of the tblh and subsequently cause errors if used again by the main routine. as a rule it is recommended that simultaneous use of the table read instructions should be avoided. however, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. note that all table related instructions require two instruction cycles to complete their operation. in circuit programming the provision of flash type program memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. as an additional convenience, holtek has provided a means of programming the microcontroller in-circuit using a rev. 1.50 36 march 06 , 2012 rev. 1.50 37 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro 5-pin interface. this provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. this enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. mcu programming pins function pa0 serial data input/output pa2 serial clock res device reset v dd power supply v ss ground the program memory and eeprom data memory can both be programmed serially in-circuit using this 5-wire interface. data is downloaded and uploaded serially on a single pin with an additional line for the clock. two additional lines are required for the power supply and one line for the reset. the technical details regarding the in-circuit programming of the devices are beyond the scope of this document and will be supplied in supplementary literature. during the programming process the res pin will be held low by the programmer disabling the normal operation of the microcontroller and taking control of the pa0 and pa2 i/o pins for data and clock programming purposes. the user must there take care to ensure that no other outputs are connected to these two pins. table read program example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address mov tblp,a ; is referenced mov a,07h ; initialise high table pointer tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address 706h transferred to tempreg1 and tblh dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer data at program ; memory address 705h transferred to tempreg2 and tblh in this ; example the data 1ah is transferred to tempreg1 and data 0fh to ; register tempreg2 : : org 700h ; sets initial address of program memory dc 00ah, 00bh, 00ch, 00dh, 00eh, 00fh, 01ah, 01bh : : ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 36 march 06 , 2012 rev. 1.50 37 march 06 , 2012 note: * may be resistor or capacitor. the resistance of * must be greater than 1k or the capacitance of * must be less than 1nf. programmer pin mcu pins res pb0 data pa0 clk pa2 programmer and mcu pins ram data memory the data memory is a volatile area of 8-bit wide ram internal memory and is the location where temporary information is stored. divided into three sections, the frst of these is an area of ram where special function registers are located. these registers have fxed locations and are necessary for correct operation of the device. many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. the second area of data memory is reserved for general purpose use. all locations within this area are read and write accessible under program control. the third area is reserved for the lcd memory. this special area of data memory is mapped directly to the lcd display so data written into this memory area will directly affect the displayed data. the addresses of the lcd memory area overlap those in the general purpose data memory area. switching between the different data memory banks is achieved by setting the bank pointer to the correct value. structure the data memory is subdivided into several banks, all of which are implemented in 8-bit wide ram. the data memory located in bank 0 is subdivided into two sections, the special purpose data memory and the general purpose data memory. the start address of the data memory for all devices is the address 00h. registers which are common to all microcontrollers, such as acc, pcl, etc., have the same data memory address. the lcd memory is mapped into bank 1. the banks 2 to 5 contain only general purpose data memory for those devices with larger data memory capacities. as the special purpose data memory registers are mapped into all bank areas, they can subsequently be accessed from any bank location. rev. 1.50 38 march 06 , 2012 rev. 1.50 39 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro device capacity banks ht67f30 128x8 0: 80h~ffh 1: 80h~98h ht67f40 256x8 0: 80h~ffh 1: 80h~a0h 2: 80h~ffh HT67F50 384x8 0: 80h~ffh 1: 80h~a8h 2: 80h~ffh 3: 80h~ffh ht67f60 640x8 0: 80h~ffh 1: 80h~b8h 2: 80h~ffh 3: 80h~ffh 4: 80h~ffh 5: 80h~ffh d ? ata memory structure C ht67f30/40/50/60 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 38 march 06 , 2012 rev. 1.50 39 march 06 , 2012 ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ? ? ??? ????????? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ?? ? ht67f30 special purpose data memory rev. 1.50 40 march 06 , 2012 rev. 1.50 41 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ? ? ? ? ? ? ? ? ? ht67f40 special purpose data memory ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 40 march 06 , 2012 rev. 1.50 41 march 06 , 2012 ? ? ? ? ? ? ? ? ? ? ? ? HT67F50 special purpose data memory rev. 1.50 42 march 06 , 2012 rev. 1.50 43 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ? ? ? ? ? ? ? ? ? ? ? ? ? ht67f60 special purpose data memory ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 42 march 06 , 2012 rev. 1.50 43 march 06 , 2012 special function register description most of the special function register details will be described in the relevant functional section; however several registers require a separate description in this section. indirect addressing registers C iar0, iar1 the indirect addressing registers, iar0 and iar1, although having their locations in normal ram register space, do not actually physically exist as normal registers. the method of indirect addressing for ram data manipulation uses these indirect addressing registers and memory pointers, in contrast to direct memory addressing, where the actual memory address is specifed. actions on the iar0 and iar1 registers will result in no actual read or write operation to these registers but rather to the memory location specifed by their corresponding memory p ointers, mp0 or mp1. acting as a pair, iar0 and mp0 can together access data from bank 0 while the iar1 and mp1 register pair can access data from any bank. as the indirect addressing registers are not physically implemented, reading the indirect addressing registers indirectly will return a result of 00h and writing to the registers indirectly will result in no operation. memory pointers C mp0, mp1 two memory pointers, known as mp0 and mp1 are provided. these memory pointers are physically implemented in the data memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. when any operation to the relevant indirect addressing registers is carried out, the actual address that the microcontroller is directed to, is the address specifed by the related memory pointer. mp0, together with indirect addressing register, iar0, are used to access data from bank 0, while mp1 and iar1 are used to access data from all banks according to bp register. direct addressing can only be used with bank 0, all other banks must be addressed indirectly using mp1 and iar1. note that for the ht67f30 device, bit 7 of the memory pointers is not required to address the full memory space. when bit 7 of the memory pointers for ht67f30 device is read, a value of 1 will be returned. the following example shows how to clear a section of four data memory locations already defned as locations adres1 to adres4. indirect addressing program example data .section data adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; accumulator loaded with frst ram address mov mp0,a ; setup memory pointer with frst ram address loop: clr iar0 ; clear the data at address defned by mp0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: the important point to note here is that in the example shown a bove, no reference is made to specifc ram addresses. rev. 1.50 44 march 06 , 2012 rev. 1.50 45 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro bank pointer C bp depending upon which device is used, the program and data memory are divided into several banks. selecting the required program and data memory area is achieved using the bank pointer. bit 5 of the bank pointer is used to select program memory bank 0 or 1, while bits 0~2 are used to select data memory banks 0~5. the data memory is initialised to bank 0 after a reset, except for a wdt time-out reset in the power down mode, in which case, the data memory bank remains unaffected. it should be noted that the special function data memory is not affected by the bank selection, which means that the special function registers can be accessed from within any bank. directly addressing the data memory will always result in bank 0 being accessed irrespective of the value of the bank pointer. accessing data from banks other than bank 0 must be implemented using indirect addressing. as both the program memory and data memory share the same bank pointer register, care must be taken during programming. device bit 7 6 5 4 3 2 1 0 ht67f30 dmbp0 ht67f40 dmbp1 dmbp0 HT67F50 dmbp1 dmbp0 ht67f60 pmbp0 dmbp2 dmbp1 dmbp0 bp registers list bp register ht67f30 bit 7 6 5 4 3 2 1 0 name dmbp0 r/w r/w por 0 bit 7 ~ 3 unimplemented, read as "0" bit 0 dmbp0 : select data memory banks 0: bank 0 1: bank 1 ht67f40 bit 7 6 5 4 3 2 1 0 name dmbp1 dmbp0 r/w r/w r/w por 0 0 bit 7 ~ 2 unimplemented, read as "0" bit 1 ~ 0 dmbp1, dmbp0 : select data memory banks 00: bank 0 01: bank 1 10: bank 2 11: undefned ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 44 march 06 , 2012 rev. 1.50 45 march 06 , 2012 HT67F50 bit 7 6 5 4 3 2 1 0 name dmbp1 dmbp0 r/w r/w r/w por 0 0 bit 7 ~ 2 unimplemented, read as "0" bit 1 ~ 0 dmbp1, dmbp0 : select data memory banks 00: bank 0 01: bank 1 10: bank 2 11: bank 3 ht67f60 bit 7 6 5 4 3 2 1 0 name pmbp0 dmbp2 dmbp1 dmbp0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 6 unimplemented, read as "0" bit 5 pmbp0 : select program memory banks 0: bank 0, program memory address is from 0000h ~ 1fffh 1: bank 1, program memory address is from 2000h ~ 2fffh bit 4 ~ 3 unimplemented, read as "0" bit 2 ~ 0 dmbp2 ~ dmbp0 : select data memory banks 000: bank 0 001: bank 1 010: bank 2 011: bank 3 100: bank 4 101: bank 5 110~111: undefned accumulator C acc the accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the alu. the accumulator is the place where all intermediate results from the alu are stored. without the accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the data memory resulting in higher programming and timing overheads. data transfer operations usually involve the temporary storage function of the accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the accumulator as no direct transfer between two registers is permitted. program counter low register C pcl to provide additional program control functions, the low byte of the program counter is made accessible to programmers by locating it within the special purpose area of the data memory. by manipulating this register, direct jumps to other program locations are easily implemented. loading a value directly into this pcl register will cause a jump to the specifed program memory location, however, as the register is only 8-bit wide, only jumps within the current program memory page are permitted. when such operations are used, note that a dummy cycle will be inserted. rev. 1.50 46 march 06 , 2012 rev. 1.50 47 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro look-up table registers C tblp, tbhp, tblh these three special function registers are used to control operation of the look-up table which is stored in the program memory. tblp and tbhp are the table pointer and indicates the location where the table data is located. their value must be setup before any table read commands are executed. their value can be changed, for example using the inc or dec instructions, allowing for easy table data pointing and reading. tblh is the location where the high order byte of the table data is stored after a table read data instruction has been executed. note that the lower order table data byte is transferred to a user defned location. status register C status this 8-bit register contains the zero fag (z), carry fag (c), auxiliary carry fag (ac), overfow fag (ov), power down fag (pdf), and watchdog time-out fag (to). these arithmetic/logical operation and system management fags are used to record the status and operation of the microcontroller . with the exception of the to and pdf fags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flag. in addition, operations related to the status register may give different results due to the different instruction operations. the to fag can be affected only by a system power-up, a wdt time-out or by executing the clr wdt or halt instruction. the pdf fag is affected only by executing the halt or clr wdt instruction or during a system power-up. the z, ov, ac and c fags generally refect the status of the latest operations. c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pdf is cleared by a system power-up or executing the clr wdt instruction. pdf is set by executing the halt instruction. to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. in addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. if the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 46 march 06 , 2012 rev. 1.50 47 march 06 , 2012 status register bit 7 6 5 4 3 2 1 0 name to pdf ov z ac c r/w r r r/w r/w r/w r/w por 0 0 x x x x x unknown bit 7, 6 unimplemented, read as 0 bit 5 to : watchdog time-out fag 0: after power up or executing the clr wdt or halt instruction 1: a watchdog time-out occurred. bit 4 pdf : power down fag 0: after power up or executing the clr wdt instruction 1: by executing the halt instruction bit 3 ov : overfow fag 0: no overfow 1: an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. bit 2 z : zero fag 0: the result of an arithmetic or logical operation is not zerot 1: the result of an arithmetic or logical operation is zero bit 1 ac : auxiliary fag 0: no auxiliary carry 1: an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction bit 0 c : carry fag 0: no carry-out 1: an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation c is also affected by a rotate through carry instruction. rev. 1.50 48 march 06 , 2012 rev. 1.50 49 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro eeprom data memory all devices contain an area of internal eeprom data memory. eeprom, which stands for electrically erasable programmable read only memory, is by its nature a non-volatile form of re- programmable memory, with data retention even when its power supply is removed. by incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. the availability of eeprom storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. the process of reading and writing data to the eeprom memory has been reduced to a very trivial affair. eeprom data memory structure the eeprom data memory capacity varies from 64x8 to 256x 8 bits, according to the device selected. unlike the program memory and ram data memory, the eeprom data memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. read and write operations to the eeprom are carried out in single byte operations using an address and data register in bank 0 and a single control register in bank 1. device capacity address ht67f30 64x8 00h ~ 3fh ht67f40 128x8 00h ~ 7fh HT67F50/ht67f60 256x8 00h ~ ffh eeprom registers three registers control the overall operation of the internal eeprom data memory. these are the address register, eea, the data register, eed and a single control register, eec. as both the eea and eed registers are located in bank 0, they can be directly accessed in the same was as any other special function register. the eec register however, being located in bank1, cannot be directly addressed directly and can only be read from or written to indirectly using the mp1 memory pointer and indirect addressing register, iar1. because the eec control register is located at address 40h in bank 1, the mp1 memory pointer must frst be set to the value 40h and the bank pointer register, bp, set to the value, 01h, before any operations on the eec register are executed. eeprom register list ht67f30 name bit 7 6 5 4 3 2 1 0 eea d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd ht67f40 name bit 7 6 5 4 3 2 1 0 eea d6 d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 48 march 06 , 2012 rev. 1.50 49 march 06 , 2012 HT67F50/ht67f60 name bit 7 6 5 4 3 2 1 0 eea d7 d6 d5 d4 d3 d2 d1 d0 eed d7 d6 d5 d4 d3 d2 d1 d0 eec wren wr rden rd eea register ht67f30 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por x x x x x x x unknown bit 7 ~ 6 unimplemented, read as 0 bit 5 ~ 0 data eeprom address data eeprom address bit 5 ~ bit 0 ht67f40 bit 7 6 5 4 3 2 1 0 name d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x unknown bit 7 unimplemented, read as 0 bit 6 ~ 0 data eeprom address data eeprom address bit 6 ~ bit 0 HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown bit 7 ~ 0 data eeprom address data eeprom address bit 7 ~ bit 0 rev. 1.50 50 march 06 , 2012 rev. 1.50 51 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro eec register bit 7 6 5 4 3 2 1 0 name wren wr rden rd r/w r/w r/w r/w r/w por 0 0 0 0 bit 7 ~ 4 unimplemented, read as 0 bit 3 wren : data eeprom write enable 0: disable 1: enable this is the data eeprom write enable bit which must be set high before data eeprom write operations are carried out. clearing this bit to zero will inhibit data eeprom write operations. bit 2 wr : eeprom write control 0: write cycle has fnished 1: activate a write cycle this is the data eeprom write control bit and when set high by the application program will activate a write cycle. this bit will be automatically reset to zero by the hardware after the write cycle has fnished. setting this bit high will have no effect if the wren has not frst been set high. bit 1 rden : data eeprom read enable 0: disable 1: enablez this is the data eeprom read enable bit which must be set high before data eeprom read operations are carried out. clearing this bit to zero will inhibit data eeprom read operations. bit 0 rd : eeprom read control 0: read cycle has fnished 1: activate a read cycle this is the data eeprom read control bit and when set high by the application program will activate a read cycle. this bit will be automatically reset to zero by the hardware after the read cycle has fnished. setting this bit high will have no effect if the rden has not frst been set high. note: the wren, wr, rden and rd can not be set to 1 at the same time in one instruction. the wr and rd can not be set to 1 at the same time. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 50 march 06 , 2012 rev. 1.50 51 march 06 , 2012 reading data from the eeprom to read data from the eeprom, the read enable bit, rden, in the eec register must frst be set high to enable the read function. the eeprom address of the data to be read must then be placed in the eea register. if the rd bit in the eec register is now set high, a read cycle will be initiated. setting the rd bit high will not initiate a read operation if the rden bit has not been set. when the read cycle terminates, the rd bit will be automatically cleared to zero, after which the data can be read from the eed register. the data will remain in the eed register until another read or write operation is executed. the application program can poll the rd bit to determine when the data is valid for reading. writing data to the eeprom to write data to the eeprom, the write enable bit, wren, in the eec register must frst be set high to enable the write function. the eeprom address of the data to be written must then be placed in the eea register and the data placed in the eed register. if the wr bit in the eec register is now set high, an internal write cycle will then be initiated. setting the wr bit high will not initiate a write cycle if the wren bit has not been set. as the eeprom write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the eeprom. detecting when the write cycle has finished can be implemented either by polling the wr bit in the eec register or by using the eeprom interrupt. when the write cycle terminates, the wr bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the eeprom. the application program can therefore poll the wr bit to determine when the write cycle has ended. write protection protection against inadvertent write operation is provided in several ways. after the device is powered-on the write enable bit in the control register will be cleared preventing any write operations. also at power-on the bank pointer, bp, will be reset to zero, which means that data memory bank 0 will be selected. as the eeprom control register is located in bank 1, this adds a further measure of protection against spurious write operations. during normal program operation, ensuring that the write enable bit in the control register is cleared will safeguard against incorrect write operations. eeprom interrupt the eeprom write interrupt is generated when an eeprom write cycle has ended. the eeprom interrupt must frst be enabled by setting the dee bit in the relevant interrupt register. however as the eeprom is contained within a multi-function interrupt, the associated multi-function interrupt enable bit must also be set. when an eeprom write cycle ends, the def request flag and its associated multi-function interrupt request fag will both be set. if the global, eeprom and multi- function interrupts are enabled and the stack is not full, a jump to the associated multi-function interrupt vector will take place. when the interrupt is serviced only the multi-function interrupt fag will be automatically reset, the eeprom interrupt fag must be manually reset by the application program. more details can be obtained in the interrupt section. rev. 1.50 52 march 06 , 2012 rev. 1.50 53 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro programming considerations care must be taken that data is not inadvertently written to the eeprom. protection can be enhanced by ensuring that the write enable bit is normally cleared to zero when not writing. also the bank pointer could be normally cleared to zero as this would inhibit access to bank 1 where the eeprom control register exist. although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. programming examples reading data from the eeprom C polling method mov a, eeprom_adres ; user defned address mov eea, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.1 ; set rden bit, enable read operations set iar1.0 ; start read cycle - set rd bit back: sz iar1.0 ; check for read cycle end jmp back clr iar1 ; disable eeprom read/write clr bp mov a, eedata ; move read data to register mov read_data, a writing data to the eeprom C polling method mov a, eepr om_adres ; user defned address mov eea, a mov a, eeprom_data ; user defned data mov eed, a mov a, 040h ; setup memory pointer mp1 mov mp1, a ; mp1 points to eec register mov a, 01h ; setup bank pointer mov bp, a set iar1.3 ; set wren bit, enable write operations set iar1.2 ; start write cycle - set wr bit back: sz iar1.2 ; check for write cycle end jmp back clr iar1 ; disable eeprom read/write clr bp ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 52 march 06 , 2012 rev. 1.50 53 march 06 , 2012 oscillator various oscillator options offer the user a wide range of functions according to their various application requirements. the flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. oscillator selections and operation are selected through a combination of confguration options and registers. oscillator overview in addition to being the source of the main system clock the oscillators also provide clock sources for the watchdog timer and time base interrupts. external oscillators requiring some external components as well as fully integrated internal oscillators, requiring no external components, are provided to form a wide range of both fast and slow system oscillators. all oscillator options are selected through the configuration options. the higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. with the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. type name freq. pins external crystal hxt 400khz~20mhz osc1/osc2 external rc erc 8mhz osc1 external clock ec 400khz~20mhz osc1 internal high speed rc hirc 4, 8 or 12mhz external low speed crystal lxt 32.768khz xt1/xt2 internal low speed rc lirc 32khz oscillator types system clock confgurations there are six methods of generating the system clock, three high speed oscillators and two low speed oscillators. the high speed oscillators are the external crystal/ceramic oscillator, external rc network oscillator, external clock and the internal 4mhz, 8mhz or 12mhz rc oscillator. the two low speed oscillators are the internal 32khz rc oscillator and the external 32.768khz crystal oscillator. selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the hlclk bit and cks2 ~ cks0 bits in the smod register and as the system clock can be dynamically selected. rev. 1.50 54 march 06 , 2012 rev. 1.50 55 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro lirc lxt low speed oscillation f h high speed oscillation hxt erc hirc ec high speed oscillation configuration option f h /64 f h /32 f h /16 f h /8 f h /4 f h /2 6 - stage prescaler f l f sub low speed oscillation configuration option f sys hlclk, cks2~cks0 bits fast wake - up from sleep mode or idle mode control (for hxt only) system clock confgurations the actual source clock used for each of the high speed and low speed oscillators is chosen via configuration options. the frequency of the slow speed or high speed system clock is also determined using the hlclk bit and cks2 ~ cks0 bits in the smod register. note that two oscillator selections must be made namely one high speed and one low speed system oscillators. it is not possible to choose a no-oscillator selection for either the high or low speed oscillator. external crystal/ ceramic oscillator C hxt the external crystal/ceramic system oscillator is one of the high frequency oscillator choices, which is selected via configuration option. for most crystal oscillator configurations, the simple connection of a crystal across osc1 and osc2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. however, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, c1 and c2. using a ceramic resonator will usually require two small value capacitors, c1 and c2, to be connected as shown for oscillation to occur. the values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer's specifcation. an additional confguration option must be setup to confgure the device according to whether the oscillator frequency is high, defned as equal to or above 1mhz, or low, which is defned as below 1mhz. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 54 march 06 , 2012 rev. 1.50 55 march 06 , 2012 ? ? ? ? crystal/resonator oscillator hxt crystal oscillator c1 and c2 values crystal frequency c1 c2 12mhz 0pf 0pf 8mhz 0pf 0pf 4mhz 0pf 0pf 1mhz 100pf 100pf 455khz (see note2) 100pf 100pf note: 1. c1 and c2 values are for guidance only. 2. xtal mode confguration option: 455khz. crystal recommended capacitor values external rc oscillator C erc using the erc oscillator only requires that a resistor, with a value between 56k and 2.4m , is connected between osc1 and v dd , and a capacitor is connected between osc1 and ground, providing a low cost oscillator configuration. it is only the external resistor that determines the oscillation frequency; the external capacitor has no infuence over the frequency and is connected for stability purposes only. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a resistance/frequency reference point, it can be noted that with an external 120k resistor connected and with a 5v voltage power supply and temperature of 25 c degrees, the oscillator will have a frequency of 8mhz within a tolerance of 2%. here only the osc1 pin is used, which is shared with i/o pin pb1, leaving pin pb2 free for use as a normal i/o pin. external rc oscillator erc rev. 1.50 56 march 06 , 2012 rev. 1.50 57 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro internal rc oscillator C hirc the internal rc oscillator is a fully integrated system oscillator requiring no external components. the internal rc oscillator has three fxed frequencies of either 4mhz, 8mhz or 12mhz. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of either 3v or 5v and at a temperature of 25 c degrees, the fxed oscillation frequency of 4mhz, 8mhz or 12mhz will have a tolerance within 2%. note that if this internal system clock option is selected, as it requires no external pins for its operation, i/o pins pb1 and pb2 are free for use as normal i/o pins. external 32.768khz crystal oscillator C lxt the external 32.768khz crystal system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. this clock source has a fxed frequency of 32.768khz and requires a 32.768khz crystal to be connected between pins xt1 and xt2. the external resistor and capacitor components connected to the 32.768khz crystal are necessary to provide oscillation. for applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. during power-up there is a time delay associated with the lxt oscillator waiting for it to start-up. when the microcontroller enters the sleep or idle mode, the system clock is switched off to stop microcontroller activity and to conserve power. however, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the sleep or idle mode. to do this, another clock, independent of the system clock, must be provided. however, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, c1 and c2. the exact values of c1 and c2 should be selected in consultation with the crystal or resonator manufacturer specification. the external parallel feedback resistor, rp, is required. some confguration options determine if the xt1/xt2 pins are used for the lxt oscillator or as i/o pins. if the lxt oscillator is not used for any clock source, the xt1/xt2 pins can be used as normal i/o pins. if the lxt oscillator is used for any clock source, the 32.768khz crystal should be connected to the xt1/xt2 pins. ? ? ? ? ? ?- ? ? ? external lxt oscillator ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 56 march 06 , 2012 rev. 1.50 57 march 06 , 2012 lxt oscillator c1 and c2 values crystal frequency c1 c2 32.768khz 10pf 10pf note:1. c1 a nd c2 values are for guidance only. 2. r p =5m ~10m is recommended. 32.768khz crystal recommended capacitor values lxt oscillator low power function the lxt oscillator can function in one of two modes, the quick start mode and the low power mode. the mode selection is executed using the lxtlp bit in the tbc register. lxtlp bit lxt mode 0 quick start 1 low-power after power on the lxtlp bit will be automatically cleared to zero ensuring that the lxt oscillator is in the quick start operating mode. in the quick start mode the lxt oscillator will power up and stabilise quickly. however, after the lxt oscillator has fully powered up it can be placed into the low-power mode by setting the lxtlp bit high. the oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the lxt oscillator start-up. in power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the lxtlp bit high about 2 seconds after power-on. it should be noted that, no matter what condition the lxtlp bit is set to, the lxt oscillator will always function normally, the only difference is that it will take more time to start up if in the low- power mode. internal 32khz oscillator C lirc the internal 32khz system oscillator is one of the low frequency oscillator choices, which is selected via confguration option. it is a fully integrated rc oscillator with a typical frequency of 32khz at 5v, requiring no external components for its implementation. device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the infuence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. as a result, at a power supply of 5v and at a temperature of 25 c degrees, the fxed oscillation frequency of 32khz will have a tolerance within 10%. external clock C ec the system clock can also be supplied by an externally supplied clock giving users a method of synchronizing their external hardware to the microcontroller operation. this is selected using a confguration option and supplying the clock on pin osc1. pin osc2 should be left foating if the external oscillator is used. the internal oscillator circuit contains a filter circuit to reduce the possibility of erratic operation due to noise on the oscillator pin, however as the filter circuit consumes a certain amount of power, a oscillator confguration option exists to turn this flter off. not using the internal filter should be considered in power sensitive applications and where the externally supplied clock is of a high integrity and supplied by a low impedance source. supplementary oscillators the low speed oscillators, in addition to providing a system clock source are also used to provide a clock source to two other device functions. these are the watchdog timer, the lcd driver and the time base interrupts. rev. 1.50 58 march 06 , 2012 rev. 1.50 59 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro operating modes and system clocks present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conficting requirements that are especially true in battery powered portable applications. the fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. as holtek has provided these devices with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. system clocks the device has many different clock sources for both the cpu and peripheral function operation. by providing the user with a wide range of clock options using configuration options and register programming, a clock system can be confgured to obtain maximum application performance. the main system clock, can come from either a high frequency, f h , or low frequency, f l , source, and is selected using the hlclk bit and cks2~cks0 bits in the smod register. the high speed system clock can be sourced from either an hxt, erc, ec or hirc oscillator, selected via a confguration option. the low speed system clock source can be sourced from internal clock f l. if f l is selected then it can be sourced by either the lxt or lirc oscillators, selected via a confguration option. the other choice, which is a divided version of the high speed system oscillator has a range of f h /2~f h /64. there are two additional internal clocks for the peripheral circuits, the substitute clock, f sub , and the time base clock, f tbc . each of these internal clocks are sourced by either the lxt or lirc oscillators, selected via confguration options. the f sub clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 58 march 06 , 2012 rev. 1.50 59 march 06 , 2012 tbck configuration option time base wdt lirc lxt f h f h /64 f h /32 f h /16 f h /8 f h /4 f h /2 6 - stage prescaler f l f sub low speed oscillation configuration option f sys hlclk, cks2~cks0 bits fast wake - up from sleep mode or idle mode control (for hxt only) f tbc f sys /4 f tb f sys /4 f sub f s f sub 4khz lcd driver f sub clock source selection spi/spia f sys 8 high speed oscillation hxt erc hirc ec high speed oscillation configuration option low speed oscillation system clock confgurations note: when the system clock source f sys is switched to f l from f h , the high speed oscillation will stop to conserve the power. thus there is no f h ~f h /64 for peripheral circuit to use. together with f sys /4 it is also used as one of the clock sources for the watchdog timer. the f tbc clock is used as a source for the time base interrupt functions and for the tms. the f sub is used as the lcd source. rev. 1.50 60 march 06 , 2012 rev. 1.50 61 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro system operation modes there are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. there are two modes allowing normal operation of the microcontroller, the normal mode and slow mode. the remaining four modes, the sleep0, sleep1, idle0 and idle1 mode are used when the microcontroller cpu is switched off to conserve power. operation mode description cpu f sys f sub f s f tbc normal mode on f h ~ f h /64 on on on slow mode on f l on on on idle0 mode off off on on/off on idle1 mode off on on on on sleep0 mode off off off off off sleep1 mode off off on on off normal mode as the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. this mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the hxt, erc, ec or hirc oscillators. the high speed oscillator will however frst be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the cks2~cks0 and hlclk bits in the smod register. although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. slow mode this is also a mode where the microcontroller operates normally although now with a slower speed clock source. the clock source used will be from one of the low speed oscillators, either the lxt or the lirc. running the microcontroller in this mode allows it to run with much lower operating currents. in the slow mode, the f h is off. sleep0 mode the sleep mode is entered when an halt instruction is executed and when the idlen bit in the smod register is low. in the sleep0 mode the cpu will be stopped, and the f sub and f s clocks will be stopped too, and the watchdog timer function is disabled. in this mode, the lvden is must set to "0". if the lvden is set to "1", it won't enter t he sleep0 mode. sleep1 mode the sleep mode is entered when an halt instruction is e xecuted and when the idlen bit in the smod register is low. in the sleep1 mode the cpu will be stopped. however the f sub and f s clocks will continue to operate if the lvden is "1" or the watchdog timer function is enabled and if its clock source is chosen via confguration option to co me from the f sub . idle0 mode the idle0 mode is entered when a halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is low. in the idle0 mode the system oscillator will be inhibited from driving the cpu but some peripheral functions will remain operational such as the watchdog timer, tms and lcd driver. in the idle0 mode, the system oscillator will be stopped. in the idle0 mode the watchdog timer clock, f s , will either be on or off depending upon the f s clock source. if the source is f sys /4 then the f s clock will be off, and if the source co mes from f sub then f s will be on. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 60 march 06 , 2012 rev. 1.50 61 march 06 , 2012 idle1 mode the idle1 mode is entered when an halt instruction is executed and when the idlen bit in the smod register is high and the fsyson bit in the wdtc register is high. in the idle1 mode the system oscillator will be inhibited from driving the cpu but may continue to provide a clock source to keep some peripheral functions operational such as the watchdog timer, tms, lcd driver, spia and sim. in the idle1 mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. in the idle1 mode the watchdog timer clock, f s , will be on. if the source is f sys /4 then the f s clock will be on, and if the source comes from f sub then f s will be on. control register a single register, smod, is used for overall control of the internal clocks within the device. smod register bit 7 6 5 4 3 2 1 0 name cks2 cks1 cks0 fsten lto hto idlen hlclk r/w r/w r/w r/w r/w r r r/w r/w por 0 0 0 0 0 0 1 1 bit 7~5 cks2~cks0 : the system clock selection when hlclk is "0" 000: f l (f lxt or f lirc ) 001: f l (f lxt or f lirc ) 010: f h /64 011: f h /32 100: f h /16 101: f h /8 110: f h /4 111: f h /2 these three bits are used to select which clock is used as the system clock source. in addition to the system clock source, which can be either the lxt or lirc, a divided version of the high speed system oscillator can also be chosen as the system clock source. bit 4 fsten : fast wake-up control (only for hxt) 0: disable 1: enable this is the fast wake-up control bit which determines if the f sub clock source is initially used after the device wakes up. when the bit is high, the f sub clock source can be used as a temporary system clock to provide a faster wake up time as the f sub clock is available. bit 3 lto : low speed system oscillator ready fag 0: not ready 1: ready this is the low speed system oscillator ready fag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. the fag will be low when in the sleep0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the lxt oscillator is used and 1~2 clock cycles if the lirc oscillator is used. bit 2 hto : high speed system oscillator ready fag 0: not ready 1: ready rev. 1.50 62 march 06 , 2012 rev. 1.50 63 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro this is the high speed system oscillator ready fag which indicates when the high speed system oscillator is stable. this flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. therefore this flag will always be read as "1" by the application program after device power-on. the fag will be low when in the sleep or idle0 mode but after a wake-up has occurred, the fag will change to a high level after 1024 clock cycles if the hxt oscillator is used and after 15~16 clock cycles if the erc or hirc oscillator is used. bit 1 idlen : idle mode control 0: disable 1: enable this is the idle mode control bit and determines what happens when the halt instruction is executed. if this bit is high, when a halt instruction is executed the device will enter the idle mode. in the idle1 mode the cpu will stop running but the system clock will continue to keep the peripheral functions operational, if fsyson bit is high. if fsyson bit is low, the cpu and the system clock will all stop in idle0 mode. if the bit is low the device will enter the sleep mode when a halt instruction is executed. bit 0 hlclk : system clock selection 0: f h /2 ~ f h /64 or f l 1: f h this bit is used to select if the f h clock or the f h /2 ~ f h /64 or f l clock is used as the system clock. when the bit is high the f h clock will be selected and if low the f h /2 ~ f h /64 or f l clock will be selected. when system clock switches from the f h clock to the f l clock and the f h clock will be automatically switched off to conserve power. fast wake-up to minimise power consumption the device can enter the sleep or idle0 mode, where the system clock source to the device will be stopped. however when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. to ensure the device is up and running as fast as possible a fast wake-up function is provided, which allows f sub , namely either the lxt or lirc oscillator, to act as a temporary clock to frst drive the system until the original system oscillator has stabilised. as the clock source for the fast wake-up function is f sub , the fast wake-up function is only available in the sleep1 and idle0 modes. when the device is woken up from the sleep0 mode, the fast wake-up function has no effect because the f sub clock is stopped. the fast wake-up enable/disable function is controlled using the fsten bit in the smod register. if the hxt oscillator is selected as the normal mode system clock, and if the fast wake-up function is enabled, then it will take one to two t sub clock cycles of the lirc or lxt oscillator for the system to wake-up. the system will then initially run under the f sub clock source until 1024 hxt clock cycles have elapsed, at which point the hto fag will switch high and the system will switch over to operating from the hxt oscillator. if the erc or ec or hirc oscillators or lirc oscillator is used as the system oscillator then it will take 15~16 clock cycles of the erc or ec or hirc or 1~2 cycles of the lirc to wake up the system from the sleep or idle0 mode. the fast wake-up bit, fsten will have no effect in these cases. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 62 march 06 , 2012 rev. 1.50 63 march 06 , 2012 system oscillator fsten bit wake-up time (sleep0 mode) wake-up time (sleep1 mode) wake-up time (idle0 mode) wake-up time (idle1 mode) hxt 0 1024 hxt cycles 1024 hxt cycles 1~2 hxt cycles 1 1024 hxt cycles 1~2 f sub cycles (system runs with f sub frst for 1024 hxt cycles and then switches over to run with the hxt clock) 1~2 hxt cycles erc x 15~16 erc cycles 15~16 erc cycles 1~2 erc cycles ec x 15~16 ec cycles 15~16 ec cycles 1~2 ec cycles hirc x 15~16 hirc cycles 15~16 hirc cycles 1~2 hirc cycles lirc x 1~2 lirc cycles 1~2 lirc cycles 1~2 lirc cycles lxt x 1024 ltx cycles 1024 lxt cycles 1~2 lxt cycles wake-up times note that if the watchdog timer is disabled, which means that the lxt and lirc are all both off, then there will be no fast wake-up function available when the device wakes-up from the sleep0 mode. ? ? ?? ? ? - ? ? ? - ? ? rev. 1.50 64 march 06 , 2012 rev. 1.50 65 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro operating mode switching and wake-up the device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. in this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. in simple terms, mode switching between the normal mode and slow mode is executed using the hlclk bit and cks2~cks0 bits in the smod register while mode switching from the normal/slow modes to the sleep/idle modes is executed via the halt instruction. when a halt instruction is executed, whether the device enters the idle mode or the sleep mode is determined by the condition of the idlen bit in the smod register and fsyson in the wdtc register. when the hlclk bit switches to a low level, which implies that clock source is switched from the high speed clock source, f h , to the clock source, f h /2~f h /64 or fl. if the clock is from the f l , the high speed clock source will stop running to conserve power. when this happens it must be noted that the f h /16 and f h /64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the tms and the sim. the accompanying fowchart shows what happens when the device moves between the various operating modes. normal mode to slow mode switching when running in the normal mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the slow mode by set the hlclk bit to "0" and set the cks2~cks0 bits to "000" or "001" in the smod register. this will then use the low speed system oscillator which will consume less power. users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. the slow mode is sourced from the lxt or the lirc oscillators and therefore requires these oscillators to be stable before full mode switching occurs. this is monitored using the lto bit in the smod register. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 64 march 06 , 2012 rev. 1.50 65 march 06 , 2012 ? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ? ?- ?? ? ? - ?? ? ? ? ? ? ? ?- ?? ?? -? ? ? ? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ?? ?? ? - ?? ? ? ? ? ? ?? ?? ? - ? ?? ? ? ? ? ?? ?? ? - ?? ? rev. 1.50 66 march 06 , 2012 rev. 1.50 67 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro slow mode to normal mode switching in slow mode the system uses eit her the lxt or lirc low speed system oscillator. to switch back to the normal mode, where the high speed system oscillator is used, the hlclk bit should be set to "1" or hlclk bit is "0", but cks2~cks0 is set to "010", "011", "100", "101", "110" or "111". as a certain amount of time will be required for the high frequency clock to stabilise, the status of the hto bit is checked. the amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. entering the sleep0 mode there is only one way for the device to enter the sleep0 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt and lvd both off. when this instruction is executed under the conditions described above, the following will occur: the system clock, wdt clock and time base clock will be stopped and the application program will stop at the "halt" instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and stopped no matter if the wdt clock source originates from the f sub clock or from the system clock. the i/o ports will maintain their present conditions. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the sleep1 mode there is only one way for the device to enter the sleep1 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "0" and the wdt or lvd on. when this instruction is executed under the conditions described above, the following will occur: the system clock and time base clock will be stopped and the application program will stop at the "halt" instruction, but the wdt or lvd will remain with the clock source coming from the f sub clock. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock as the wdt is enabled. the i/o ports will maintain their present conditions. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 66 march 06 , 2012 rev. 1.50 67 march 06 , 2012 entering the idle0 mode there is only one way for the device to enter the idle0 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in wdtc register equal to "0". when this instruction is executed under the conditions described above, the following will occur: the system clock will be stopped and the application program will stop at the "halt" instruction, but the time base clock and f sub clock will be on. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present conditions. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. entering the idle1 mode there is only one way for the device to en ter the idle1 mode and that is to execute the "halt" instruction in the application program with the idlen bit in smod register equal to "1" and the fsyson bit in wdtc register equal to "1". when this instruction is executed under the with conditions described above, the following will occur: the system clock and time base clock and f sub clock will be on and the application program will stop at the "halt" instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt is enabled regardless of the wdt clock source which originates from the f sub clock or from the system clock. the i/o ports will maintai n their present conditions. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleare d. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the idle1 mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lxt or lirc oscillator. in the idle1 mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. rev. 1.50 68 march 06 , 2012 rev. 1.50 69 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the "halt" instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the "halt" instruction. if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt" instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is fnally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request flag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. programming considerations the hxt and lxt oscillators both use the same sst counter. for example, if the system is woken up from the sleep0 mode and both the hxt and lxt oscillators need to start-up from an off state. the lxt oscillator uses the sst counter after hxt oscillator has fnished its sst period. if the device is woken up from the sleep0 mode to the normal mode, the high speed system oscillator needs an sst period. the device will execute frst instruction after hto is "1". at this time, the lxt oscillator may not be stability if f sub is from lxt oscillator. the same situation occurs in the power-on state. the lxt oscillator is not ready yet when the first instruction is executed. if the device is woken up from the sleep1 mode to normal mode, and the system clock source is from hxt oscillator and fsten is "1" , the system clock can be switched to the lxt or lirc oscillator after wake up. there are peripheral functions, such as wdt, tms and spia, lcd driver and sim, for which the f sys is used. if the system clock source is switched from f h to f l , the clock source to the peripheral functions mentioned above will change accordingly. the on/off condition of f sub and f s depends upon whether the wdt is enabled or disabled as the wdt clock source is selected from f sub . ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 68 march 06 , 2012 rev. 1.50 69 march 06 , 2012 watchdog timer the watchdog timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. watchdog timer clock source the watchdog timer clock source is provided by the internal clock, f s , which is in turn supplied by one of two sources selected by confguration option: f sub or f sys /4. the f sub clock can be sourced from either the lxt or lirc oscillators, again chosen via a confguration option. the watchdog timer source clock is then subdivided by a ratio of 2 8 to 2 15 to give longer timeouts, the actual value being chosen using the ws2~ws0 bits in the wdtc register. the lirc internal oscillator has an approximate period of 32khz at a supply voltage of 5v. however, it should be noted that this specifed internal clock period can vary with v dd , temperature and process variations. the lxt oscillator is supplied by an external 32.768khz crystal. the other watchdog timer clock source option is the f sys /4 clock. the watchdog timer clock source can originate from its own internal lirc oscillator, the lxt oscillator or f sys /4. it is divided by a value of 28 to 215, using the ws2~ws0 bits in the wdtc register to obtain the required watchdog timer time-out period. watchdog timer control register a single register, wdtc, controls the required timeout period as well as the enable/disable operation. this register together with several confguration options control the overall operation of the watchdog timer. wdtc register bit 7 6 5 4 3 2 1 0 name fsyson ws2 ws1 ws0 wdten3 wdten2 wdten1 wdten0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 1 1 1 1 0 1 0 bit 7 fsyson : f sys control in idle mode 0: disable 1: enable bit 6 ~ 4 ws2, ws1, ws0 : wdt time-out period selection 000: 256/f s 001: 512/f s 010: 1024/f s 011: 2048/f s 100: 4096/f s 101: 8192/f s 110: 16384/f s 111: 32768/f s these three bits determine the division ratio of the watchdog timer source clock, which in turn determines the timeout period. bit 3 ~ 0 wdten3, wdten2, wdten1, wdten0 : wdt software control 1010: disable other: enable rev. 1.50 70 march 06 , 2012 rev. 1.50 71 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro watchdog timer operation the watchdog timer operates by providing a device reset when its timer overfows. this means that in the application program and during normal operation the user has to strategically clear the watchdog timer before it overfows to prevent the watchdog timer from executing a reset. this is done using the clear watchdog instructions. if the program malfunctions for whatever reason, jumps to an unkown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the watchdog timer will overfow and reset the device. some of the watchdog timer options, such as enable/disable, clock source selection and clear instruction type are selected using confguration options. in addition to a confguration option to enable/disable the watchdog timer, there are also four bits, wdten3~wdten0, in the wdtc register to offer an additional enable/disable control of the watchdog timer. to disable the watchdog timer, as well as the confguration option being set to disable, the wdten3~wdten0 bits must also be set to a specifc value of "1010". any other values for these bits will keep the watchdog timer enabled, irrespective of the confguration enable/disable setting. after power on these bits will have the value of 1010. if the watchdog timer is used it is recommended that they are set to a value of 0101 for maximum noise immunity. note that if the watchdog timer has been disabled, then any instruction relating to its operation will result in no operation. wdt confguration option wdten3~wdten0 bits wdt wdt enable xxxx enable wdt disable except 1010 enable wdt disable 1010 disable watchdog timer enable/disable control under normal program operation, a watchdog timer time-out will initialise a device reset and set the status bit to. however, if the system is in the sleep or idle mode, when a watchdog timer time-out occurs, the to bit in the status register will be set and only the program counter and stack pointer will be reset. three methods can be adopted to clear the contents of the watchdog timer. the frst is an external hardware reset, which means a low level on the res pin, the second is using the watchdog timer software clear instructions and the third is via a halt instruction. there are two methods of using software instructions to clear the watchdog timer, one of which must be chosen by confguration option. the frst option is to use the single "clr wdt" instruction while the second is to use the two commands "clr wdt1" and "clr wdt2". for the frst option, a simple execution of clr wdt will clear the wdt while for the second option, both "clr wdt1" and "clr wdt2" must both be executed alternately to successfully clear the watchdog timer. note that for this second option, if "clr wdt1" is used to clear the watchdog timer, successive executions of this instruction will have no effect, only the execution of a "clr wdt2" instruction will clear the watchdog timer. similarly after the "clr wdt2" instruction has been executed, only a successive "clr wdt1" instruction can clear the watchdog timer. the maximum time out period is when the 2 15 division ratio is selected. as an example, with a 32.768khz lxt oscillator as its source clock, this will give a maximum watchdog period of around 1 second for the 2 15 division ratio, and a minimum timeout of 7.8ms for the 2 8 division ration. if the f sys /4 clock is used as the watchdog timer clock source, it should be noted that when the system enters the sleep or idle0 mode, then the instruction clock is stopped and the watchdog timer may lose its protecting purposes. for systems that operate in noisy environments, using the f sub clock source is strongly recommended. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 70 march 06 , 2012 rev. 1.50 71 march 06 , 2012 ? ? ?? ? ? ? ?? ? ?- ? ? ?- ? ? ? ? ? ?- ? ? ? ? ? ? ? -? -? ?? ? ? ? ? ? ? ? ? ? ?? ? watchdog timer reset and initialisation a reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. the most important reset condition is after power is frst applied to the microcontroller. in this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the frst program instruction. after this power-on reset, certain important internal registers will be set to defned states before the program commences. one of these registers is the program counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest program memory address. in addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the is running. one example of this is where after power has been applied and the is already running, the res line is forcefully pulled low. in such a case, known as a normal operation reset, some of the registers remain unchanged allowing the to proceed with normal operation after the reset line is allowed to return high. another type of reset is when the watchdog timer overflows and resets the . all types of reset operations result in different register conditions being setup. another reset exists in the form of a low voltage reset, lvr, where a full reset, similar to the res reset is implemented in situations where the power supply voltage falls below a certain threshold. reset functions there are five ways in which a reset can occur, through events occurring both internally and externally: power-on reset the most fundamental and unavoidable reset is the one that occurs after power is frst applied to the . as well as ensuring that the program memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. all the i/o port and port control registers will power up in a high condition ensuring that all pins will be frst set to inputs. power-on reset timing chart note: t rstd is power-on delay, typical time=100ms rev. 1.50 72 march 06 , 2012 rev. 1.50 73 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro res pin as the reset pin is sha red with pb.0, the reset function must be selected using a confguration option. although the has an internal rc reset function, if the v dd power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. for this reason it is recommended that an external rc network is connected to the res pin, whose additional time delay will ensure that the res pin remains low for an extended period to allow the power supply to stabilise. during this time delay, normal operation of the will be inhibited. after the res line reaches a certain voltage value, the reset delay time t rstd is invoked to provide an extra delay time after which the will begin normal operation. the abbreviation sst in the fgures stands for system start-up timer. for most applications a resistor connected between v dd and the res pin and a capacitor connected between v ss and the res pin will provide a suitable external reset circuit. any wiring connected to the res pin should be kept as short as possible to minimise any stray noise interference. for applications that operate within an environment where more noise is present the enhanced reset circuit shown is recommended. external res circuit note: * it is recommended that this component is added for added esd protection. ** it is recommended that this component is added in environments where power line noise is signifcant. more information regarding external reset circuits is located in application note ha0075e on the holtek website. pulling the res pin low using external hardware will also execute a device reset. in this case, as in the case of other resets, the program counter will reset to zero and program execution initiated from this point. res reset timing chart note: t rstd is power-on delay, typical time=100ms ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 72 march 06 , 2012 rev. 1.50 73 march 06 , 2012 low voltage reset lvr the contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a confguration option. if the supply voltage of the device drops to within a range of 0.9v~v lvr such as might occur when changing the battery, the lvr will automatically reset the device internally. the lvr includes the following specifcations: for a valid lvr signal, a low voltage, i.e., a voltage in the range between 0.9v~v lvr must exist for greater than the value t lvr specifed in the a.c. characteristics. if the low voltage state does not exceed t lvr , the lvr will ignore it and will not perform a reset function. one of a range of specifed voltage values for v lvr can be selected using confguration options. low voltage reset timing chart note: t rstd is power-on delay, typical time=100ms watchdog time-out reset during normal operation the watchdog time-out reset during normal operation is the same as a hardware res pin reset except that the watchdog time-out fag to will be set to "1". wdt time-out reset during normal operation timing chart note: t rstd is power-on delay, typical time=100ms watchdog time-out reset during sleep or idle mode the watchdog time-out reset during sleep or idle mode is a little different from other kinds of reset. most of the conditions remain unchanged except that the program counter and the stack pointer will be cleared to "0" and the to fag will be set to "1". refer to the a.c. characteristics for t sst details. wdt time-out reset during sleep or idle timing chart note: the t sst is 15~16 clock cycles if the system clock source is provided by erc or hirc. the t sst is 1024 clock for hxt or lxt. the t sst is 1~2 clock for lirc. rev. 1.50 74 march 06 , 2012 rev. 1.50 75 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro reset initial conditions the different types of reset described affect the reset fags in different ways. these fags, known as pdf and to are located in the status register and are controlled by various microcontroller operations, such as the sleep or idle mode function or watchdog timer. the reset flags are shown in the table: to pdf reset conditions 0 0 power-on reset u u res or lvr reset during normal or slow mode operation 1 u wdt time-out reset during normal or slow mode operation 1 1 wdt time-out reset during idle or sleep mode operation note: "u" stands for unchanged the following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. item condition after reset program counter reset to zero interrupts all interrupts will be disabled wdt clear after reset, wdt begins counting timer/event counter timer counter will be turned off input/output ports i/o ports will be setup as inputs, and an0~an11 in as a/d input pin. stack pointer stack pointer will point to the top of the stack the different kinds of resets all affect the internal registers of the microcontroller in different ways. to ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. the following table describes how each type of reset affects each of the microcontroller internal registers. note that where more than one package type exists the table will refect the situation for the larger package type. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 74 march 06 , 2012 rev. 1.50 75 march 06 , 2012 ht67f30 register register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu mp1 1xxx xxxx 1xxx xxxx 1xxx xxxx 1uuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh --xx xxxx --uu uuuu --uu uuuu --uu uuuu tbhp ---- -xxx ---- -uuu ---- -uuu ---- -uuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu bp ---- -000 ---- -000 ---- -000 ---- -uuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu integ ---- 0000 ---- 0000 ---- 0000 ---- uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 --00 --00 --00 --00 --00 --00 --uu --uu mfi1 -000 -000 -000 -000 -000 -000 -uuu -uuu mfi2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi3 -0-- -0-- -0-- -0-- -0-- -0-- -u-- -u-- pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pb --11 1111 --11 1111 --11 1111 --uu uuuu pbc --11 1111 --11 1111 --11 1111 --uu uuuu pc ---- --11 ---- --11 ---- --11 ---- --uu pcc ---- --11 ---- --11 ---- --11 ---- --uu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu adrl(adref=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- adrl(adref=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh(adref=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh(adref=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu adcr0 0110 -000 0110 -000 0110 -000 uuuu -uuu adcr1 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu acerl 1111 1111 1111 1111 1111 1111 uuuu uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu eea --00 0000 --00 0000 --00 0000 --uu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu simc0 1110 000- 1110 000- 1110 000- uuuu uuu- rev. 1.50 76 march 06 , 2012 rev. 1.50 77 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 uuuu uuuu spiac0 111- --0- 111- --0- 111- --0- uuu- --u- spiac1 --00 0000 --00 0000 --00 0000 --uu uuuu spiad xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pbpu --00 0000 --00 0000 --00 0000 --uu uuuu pcpu ---- --00 ---- --00 ---- --00 uuuu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu cp0c 1000 0--1 1000 0--1 1000 0--1 uuuu u--u cp1c 1000 0--1 1000 0--1 1000 0--1 uuuu u--u tmpc0 1-01 --01 1-01 --01 1-01 --01 u-uu --uu prm0 0000 ---- 0000 ---- 0000 ---- uuuu ---- prm1 -00- 0000 -00- 0000 -00- 0000 -uu- uuuu prm2 ---- -000 ---- -000 ---- -000 ---- -uuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --00 ---- --uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --00 ---- --uu tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1bh ---- --00 ---- --00 ---- --00 ---- --uu lcdctrl 000- 0000 000- 0000 000- 0000 uuu- uuuu lcdout0 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdout1 1111 1111 1111 1111 1111 1111 uuuu uuuu note: * stands for warm reset, - not implement u stands for unchanged x stands for unknown ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 76 march 06 , 2012 rev. 1.50 77 march 06 , 2012 ht67f40 register register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu tbhp ---- xxxx ---- uuuu ---- uuuu ---- uuuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu bp ---- --00 ---- --00 ---- --00 ---- --uu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu integ ---- 0000 ---- 0000 ---- 0000 ---- uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 -000 -000 -000 -000 -000 -000 -uuu -uuu mfi2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi3 -0-- -0-- -0-- -0-- -0-- -0-- -u-- -u-- pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pb --11 1111 --11 1111 --11 1111 --uu uuuu pbc --11 1111 --11 1111 --11 1111 --uu uuuu pc --11 1111 --11 1111 --11 1111 --uu uuuu pcc --11 1111 --11 1111 --11 1111 --uu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pf 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 1111 1111 1111 uuuu uuuu adrl(adref=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh(adref=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh(adref=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu adcr0 0110 -000 0110 -000 0110 -000 uuuu -uuu adcr1 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu ancsr 1111 1111 1111 1111 1111 1111 uuuu uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu eea -000 0000 -000 0000 -000 0000 -uuu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu simc0 1110 000- 1110 000- 1110 000- uuuu uuu- simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 uuuu uuuu spiac0 111- --0- 111- --0- 111- --0- uuu- --u- rev. 1.50 78 march 06 , 2012 rev. 1.50 79 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) spiac1 --00 0000 --00 0000 --00 0000 --uu uuuu spiad xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pbpu --00 0000 --00 0000 --00 0000 --uu uuuu pcpu --00 0000 --00 0000 --00 0000 --uu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pfpu 0000 0000 0000 0000 0000 0000 uuuu uuuu cp0c 1000 0--1 1000 0--1 1000 0--1 uuuu u--u cp1c 1000 0--1 1000 0--1 1000 0--1 uuuu u--u tmpc0 1001 --01 1001 --01 1001 --01 uuuu --uu tmpc1 ---- --01 ---- --01 ---- --01 ---- --uu prm0 0000 0000 0000 0000 0000 0000 uuuu uuuu prm1 000- 0000 000- 0000 000- 0000 uuu- uuuu prm2 --00 0000 --00 0000 --00 0000 --uu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --00 ---- --uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --00 ---- --uu tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1bh ---- --00 ---- --00 ---- --00 ---- --uu tm2c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm2c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2rp 0000 0000 0000 0000 0000 0000 uuuu uuuu lcdctrl 000- 0000 000- 0000 000- 0000 uuu- uuuu lcdout0 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdout1 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdout2 1111 1111 1111 1111 1111 1111 uuuu uuuu note: * stands for warm reset, - not implement u stands for unchanged x stands for unknown ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 78 march 06 , 2012 rev. 1.50 79 march 06 , 2012 HT67F50 register register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp ---x xxxx ---u uuuu ---u uuuu ---u uuuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu bp ---- --00 ---- --00 ---- --00 ---- --uu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu integ ---- 0000 ---- 0000 ---- 0000 ---- uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 -000 -000 -000 -000 -000 -000 -uuu -uuu mfi2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi3 -000 -000 -000 -000 -000 -000 -uuu -uuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 11 1111 11 1111 11 1111 uu uuuu pcc 11 1111 11 1111 11 1111 uu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pf 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 1111 1111 1111 uuuu uuuu pg 11 1111 11 1111 11 1111 uu uuuu pgc 11 1111 11 1111 11 1111 uu uuuu adrl(adref=0) xxxx ---- xxxx ---- xxxx ---- u u u u - - - - adrl(adref=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh(adref=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh(adref=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu adcr0 0110 -000 0110 -000 0110 -000 uuuu -uuu adcr1 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu acerl 1111 1111 1111 1111 1111 1111 uuuu uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu rev. 1.50 80 march 06 , 2012 rev. 1.50 81 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) eea 0000 0000 0000 0000 0000 0000 uuuu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu simc0 1110 000- 1110 000- 1110 000- uuuu uuu- simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 uuuu uuuu spiac0 111- --0- 111- --0- 111- --0- uuu- --u- spiac1 --00 0000 --00 0000 --00 0000 --uu uuuu spiad xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pcpu 00 0000 00 0000 00 0000 uu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pfpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pgpu 00 0000 00 0000 00 0000 uu uuuu cp0c 1000 0--1 1000 0--1 1000 0--1 uuuu u--u cp1c 1000 0--1 1000 0--1 1000 0--1 uuuu u--u tmpc0 1001 --01 1001 --01 1001 --01 uuuu --uu tmpc1 --01 --01 --01 --01 --01 --01 --uu --uu prm0 0000 0000 0000 0000 0000 0000 uuuu uuuu prm1 000- 0000 000- 0000 000- 0000 uuu- uuuu prm2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --00 ---- --uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --00 ---- --uu tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1bh ---- --00 ---- --00 ---- --00 ---- --uu tm2c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm2c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dl 0000 0000 0000 0000 0000 0000 uuuu uuuu ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 80 march 06 , 2012 rev. 1.50 81 march 06 , 2012 register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) tm2dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2rp 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dh ---- --00 ---- --00 ---- --00 ---- --uu tm3al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3ah ---- --00 ---- --00 ---- --00 ---- --uu lcdctrl 000- 0000 000- 0000 000- 0000 uuu- uuuu lcdout0 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdout1 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdout2 1111 1111 1111 1111 1111 1111 uuuu uuuu note: * stands for warm reset, - not implement u stands for unchanged x stands for unknown rev. 1.50 82 march 06 , 2012 rev. 1.50 83 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ht67f60 register register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) mp0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu mp1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu pcl 0000 0000 0000 0000 0000 0000 0000 0000 tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu tbhp --xx xxxx --uu uuuu --uu uuuu --uu uuuu status --00 xxxx --uu uuuu --1u uuuu --11 uuuu bp --0- -000 --0- -000 --0- --000 --u- -uuu smod 0000 0011 0000 0011 0000 0011 uuuu uuuu integ 0000 0000 0000 0000 0000 0000 uuuu uuuu lvdc --00 -000 --00 -000 --00 -000 --uu -uuu intc0 -000 0000 -000 0000 -000 0000 -uuu uuuu intc1 0000 0000 0000 0000 0000 0000 uuuu uuuu intc2 0000 0000 0000 0000 0000 0000 uuuu uuuu intc3 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi0 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi1 -000 -000 -000 -000 -000 -000 -uuu -uuu mfi2 0000 0000 0000 0000 0000 0000 uuuu uuuu mfi3 -000 -000 -000 -000 -000 -000 -uuu -uuu pa 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 uuuu uuuu pe 1111 1111 1111 1111 1111 1111 uuuu uuuu pec 1111 1111 1111 1111 1111 1111 uuuu uuuu pf 1111 1111 1111 1111 1111 1111 uuuu uuuu pfc 1111 1111 1111 1111 1111 1111 uuuu uuuu pg 1111 1111 1111 1111 1111 1111 uuuu uuuu pgc 1111 1111 1111 1111 1111 1111 uuuu uuuu ph 1111 1111 1111 1111 1111 1111 uuuu uuuu phc 1111 1111 1111 1111 1111 1111 uuuu uuuu adrl(adref=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- adrl(adref=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh(adref=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu adrh(adref=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu adcr0 0110 0000 0110 0000 0110 0000 uuuu uuuu adcr1 00-0 -000 00-0 -000 00-0 -000 uu-u -uuu ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 82 march 06 , 2012 rev. 1.50 83 march 06 , 2012 register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) acerl 1111 1111 1111 1111 1111 1111 uuuu uuuu acerh ---- 1111 ---- 1111 ---- 1111 ---- uuuu wdtc 0111 1010 0111 1010 0111 1010 uuuu uuuu tbc 0011 0111 0011 0111 0011 0111 uuuu uuuu eea 0000 0000 0000 0000 0000 0000 uuuu uuuu eed 0000 0000 0000 0000 0000 0000 uuuu uuuu eec ---- 0000 ---- 0000 ---- 0000 ---- uuuu simc0 1110 000- 1110 000- 1110 000- uuuu uuu- simc1 1000 0001 1000 0001 1000 0001 uuuu uuuu simd xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu sima/simc2 0000 0000 0000 0000 0000 0000 uuuu uuuu spiac0 111- --0- 111- --0- 111- --0- uuu- --u- spiac1 --00 0000 --00 0000 --00 0000 --uu uuuu spiad xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu pawu 0000 0000 0000 0000 0000 0000 uuuu uuuu papu 0000 0000 0000 0000 0000 0000 uuuu uuuu pbpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pcpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pdpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pepu 0000 0000 0000 0000 0000 0000 uuuu uuuu pfpu 0000 0000 0000 0000 0000 0000 uuuu uuuu pgpu ---- --00 ---- --00 ---- --00 ---- --uu cp0c 1000 0--1 1000 0--1 1000 0--1 uuuu u--u cp1c 1000 0--1 1000 0--1 1000 0--1 uuuu u--u tmpc0 1001 --01 1001 --01 1001 --01 uuuu --uu tmpc1 --01 --01 --01 --01 --01 --01 --uu --uu prm0 0000 0000 0000 0000 0000 0000 uuuu uuuu prm1 0000 0000 0000 0000 0000 0000 uuuu uuuu prm2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0dh ---- --00 ---- --00 ---- --00 ---- --uu tm0al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm0ah ---- --00 ---- --00 ---- --00 ---- --uu tm1c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1c2 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1dh ---- --00 ---- --00 ---- --00 ---- --uu tm1al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm1ah ---- --00 ---- --00 ---- --00 ---- --uu tm1bl 0000 0000 0000 0000 0000 0000 uuuu uuuu rev. 1.50 84 march 06 , 2012 rev. 1.50 85 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro register reset (power on) res or lvr reset wdt time-out (normal operation) wdt time-out (idle) tm1bh ---- --00 ---- --00 ---- --00 ---- --uu tm2c0 0000 0--- 0000 0--- 0000 0--- uuuu u--- tm2c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2dh 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2ah 0000 0000 0000 0000 0000 0000 uuuu uuuu tm2rp 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c0 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3c1 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dl 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3dh ---- --00 ---- --00 ---- --00 ---- --uu tm3al 0000 0000 0000 0000 0000 0000 uuuu uuuu tm3ah ---- --00 ---- --00 ---- --00 ---- --uu lcdctrl 000- 0000 000- 0000 000- 0000 uuu- uuuu lcdout0 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdout1 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdout2 1111 1111 1111 1111 1111 1111 uuuu uuuu lcdout3 1111 1111 1111 1111 1111 1111 uuuu uuuu note: * stands for warm reset, - not implement u stands for unchanged x stands for unknown ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 84 march 06 , 2012 rev. 1.50 85 march 06 , 2012 input/output ports holtek microcontrollers offer considerable fexibility on their i/o ports. with the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an i/o structure to meet the needs of a wide range of application possibilities. the device provides bidirectional input/output lines labeled with port names pa~ph these i/o ports are mapped to the ram data memory with specifc addresses as shown in the special purpose data memory table. all of these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, which means the inputs must be ready at the t2 rising edge of instruction mov a, [m], where m denotes the port address. for output operation, all the data is latched and remains unchanged until the output latch is rewritten. i/o register list ht67f30 register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 pbpu d5 d4 d3 d2 d1 d0 pb d5 d4 d3 d2 d1 d0 pbc d5 d4 d3 d2 d1 d0 pcpu d1 d0 pc d1 d0 pcc d1 d0 pdpu d7 d6 d5 d4 d3 d2 d1 d0 pd d7 d6 d5 d4 d3 d2 d1 d0 pdc d7 d6 d5 d4 d3 d2 d1 d0 pepu d7 d6 d5 d4 d3 d2 d1 d0 pe d7 d6 d5 d4 d3 d2 d1 d0 pec d7 d6 d5 d4 d3 d2 d1 d0 rev. 1.50 86 march 06 , 2012 rev. 1.50 87 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ht67f40 register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 pbpu d5 d4 d3 d2 d1 d0 pb d5 d4 d3 d2 d1 d0 pbc d5 d4 d3 d2 d1 d0 pcpu d5 d4 d3 d2 d1 d0 pc d5 d4 d3 d2 d1 d0 pcc d5 d4 d3 d2 d1 d0 pdpu d7 d6 d5 d4 d3 d2 d1 d0 pd d7 d6 d5 d4 d3 d2 d1 d0 pdc d7 d6 d5 d4 d3 d2 d1 d0 pepu d7 d6 d5 d4 d3 d2 d1 d0 pe d7 d6 d5 d4 d3 d2 d1 d0 pec d7 d6 d5 d4 d3 d2 d1 d0 pfpu d7 d6 d5 d4 d3 d2 d1 d0 pf d7 d6 d5 d4 d3 d2 d1 d0 pfc d7 d6 d5 d4 d3 d2 d1 d0 HT67F50 register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 pbpu d7 d6 d5 d4 d3 d2 d1 d0 pb d7 d6 d5 d4 d3 d2 d1 d0 pbc d7 d6 d5 d4 d3 d2 d1 d0 pcpu d5 d4 d3 d2 d1 d0 pc d5 d4 d3 d2 d1 d0 pcc d5 d4 d3 d2 d1 d0 pdpu d7 d6 d5 d4 d3 d2 d1 d0 pd d7 d6 d5 d4 d3 d2 d1 d0 pdc d7 d6 d5 d4 d3 d2 d1 d0 pepu d7 d6 d5 d4 d3 d2 d1 d0 pe d7 d6 d5 d4 d3 d2 d1 d0 pec d7 d6 d5 d4 d3 d2 d1 d0 pfpu d7 d6 d5 d4 d3 d2 d1 d0 pf d7 d6 d5 d4 d3 d2 d1 d0 pfc d7 d6 d5 d4 d3 d2 d1 d0 pgpu d5 d4 d3 d2 d1 d0 pg d5 d4 d3 d2 d1 d0 pgc d5 d4 d3 d2 d1 d0 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 86 march 06 , 2012 rev. 1.50 87 march 06 , 2012 ht67f60 register name bit 7 6 5 4 3 2 1 0 pawu d7 d6 d5 d4 d3 d2 d1 d0 papu d7 d6 d5 d4 d3 d2 d1 d0 pa d7 d6 d5 d4 d3 d2 d1 d0 pac d7 d6 d5 d4 d3 d2 d1 d0 pbpu d7 d6 d5 d4 d3 d2 d1 d0 pb d7 d6 d5 d4 d3 d2 d1 d0 pbc d7 d6 d5 d4 d3 d2 d1 d0 pcpu d7 d6 d5 d4 d3 d2 d1 d0 pc d7 d6 d5 d4 d3 d2 d1 d0 pcc d7 d6 d5 d4 d3 d2 d1 d0 pdpu d7 d6 d5 d4 d3 d2 d1 d0 pd d7 d6 d5 d4 d3 d2 d1 d0 pdc d7 d6 d5 d4 d3 d2 d1 d0 pepu d7 d6 d5 d4 d3 d2 d1 d0 pe d7 d6 d5 d4 d3 d2 d1 d0 pec d7 d6 d5 d4 d3 d2 d1 d0 pfpu d7 d6 d5 d4 d3 d2 d1 d0 pf d7 d6 d5 d4 d3 d2 d1 d0 pfc d7 d6 d5 d4 d3 d2 d1 d0 pgpu d7 d6 d5 d4 d3 d2 d1 d0 pg d7 d6 d5 d4 d3 d2 d1 d0 pgc d7 d6 d5 d4 d3 d2 d1 d0 phpu d7 d6 d5 d4 d3 d2 d1 d0 ph d7 d6 d5 d4 d3 d2 d1 d0 phc d7 d6 d5 d4 d3 d2 d1 d0 rev. 1.50 88 march 06 , 2012 rev. 1.50 89 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro pull-high resistors many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. to eliminate the need for these external resistors, all i/o pins, when confgured as an input have the capability of being connected to an internal pull-high resistor. these pull-high resistors are selected using registers papu~phpu, and are implemented using weak pmos transistors. papu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pbpu register ht67f30/ht67f40 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pcpu register ht67f30 bit 7 6 5 4 3 2 1 0 name d1 d0 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as 0 ht67f40/HT67F50 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimplemented, read as 0 ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 88 march 06 , 2012 rev. 1.50 89 march 06 , 2012 pdpu register ht67f30/ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pepu register ht67f30/ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pfpu register ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 pgpu register HT67F50 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 phpu register ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 i/o port bit 7 ~ bit 0 pull-high control 0: disable 1: enable rev. 1.50 90 march 06 , 2012 rev. 1.50 91 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro port a wake-up the halt instruction forces the microcontroller into the sleep or idle mode which preserves power, a feature that is important for battery and other low-power applications. various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the port a pins from high to low. this function is especially suitable for applications that can be woken up via external switches. each pin on port a can be selected individually to have this wake-up feature using the pawu register. pawu register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 paw u : port a bit 7 ~ bit 0 wake-up control 0: disable 1: enable i/o port control registers each i/o port has its own control register known as pac~phc, to control the input/output configuration. with this control register, each cmos output or input can be reconfigured dynamically under software control. each pin of the i/o ports is directly mapped to a bit in its associated port control register. for the i/o pin to function as an input, the corresponding bit of the control register must be written as a 1. this will then allow the logic state of the input pin to be directly read by instructions. when the corresponding bit of the control register is written as a 0, the i/o pin will be setup as a cmos output. if the pin is currently setup as an output, instructions can still be used to read the output register. however, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. pac register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pbc register ht67f30/ht67f40 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 unimplemented, read as 0 HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 90 march 06 , 2012 rev. 1.50 91 march 06 , 2012 pcc register ht67f30 bit 7 6 5 4 3 2 1 0 name d1 d0 r/w r/w r/w por 1 1 bit 7~2 C unimplemented, read as 0 ht67f40 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 C unimplemented, read as 0 HT67F50 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 C unimplemented, read as 0 ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pdc register ht67f30/ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pec register ht67f30/ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 pfc register ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 rev. 1.50 92 march 06 , 2012 rev. 1.50 93 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro pgc register HT67F50 bit 7 6 5 4 3 2 1 0 name d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 bit 7~6 C unimplemented, read as 0 ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 phc register ht67f60 bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7~0 i/o port bit 7 ~ bit 0 input/output control 0: output 1: input pin-remapping functions the fexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these diffculties can be overcome. the way in which the pin function of each pin is selected is different for each function and a priority order is established where more than one pin function is selected simultaneously. additionally there are a series of prm0, prm1 and prm2 registers to establish certain pin functions. pin-remapping registers the limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. however by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. some devices include prm0, prm1 or prm2 registers which can select the functions of certain pins. pin-remapping register list ht67f30 register name bit 7 6 5 4 3 2 1 0 prm0 1xps1 c1xps0 c0xps1 c0xps0 prm1 tck1ps tck0ps int1ps int0ps tp1b1ps tp1b0ps prm2 tp1aps tp01ps tp00ps ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 92 march 06 , 2012 rev. 1.50 93 march 06 , 2012 ht67f40 register name bit 7 6 5 4 3 2 1 0 prm0 c1xps1 c1xps0 c0xps1 c0xps0 simps1 simps0 pckps1 pckps0 prm1 tck2ps tck1ps tck0ps int1ps int0ps tp1b1ps tp1b0ps prm2 tp21ps tp20ps tp1b2ps tp1aps tp01ps tp00ps HT67F50 register name bit 7 6 5 4 3 2 1 0 prm0 c1xps1 c1xps0 c0xps1 c0xps0 simps1 simps0 pckps1 pckps0 prm1 tck2ps tck1ps tck0ps int1ps int0ps tp1b1ps tp1b0ps prm2 tp31ps tp30ps tp21ps tp20ps tp1b2ps tp1aps tp01ps tp00ps ht67f60 register name bit 7 6 5 4 3 2 1 0 prm0 c1xps1 c1xps0 c0xps1 c0xps0 simps1 simps0 pckps1 pckps0 prm1 tck2ps tck1ps tck0ps int2ps int1ps int0ps tp1b1ps tp1b0ps prm2 tp31ps tp30ps tp21ps tp20ps tp1b2ps tp1aps tp01ps tp00ps prm0 register ht67f30 bit 7 6 5 4 3 2 1 0 name ? 1xps1 c1xps0 c0xps1 c0xps0 r/w r/w r/w r/w ? r/w por ?0 ?0 ?0 ?0 bit 7~6 c1xps1, c1xps0 : c1x pin remapping control 00: c1x on pa5 01: c1x on pe6 10: c1x on pe7 8qghqhg bit 5~4 c0xps1, c0xps0 : c0x pin remapping control 00: c0x on pa0 01: c0x on pe2 10: c0x on pe3 8qghqhg bit 3~0 unimplemented, read as 0 rev. 1.50 94 march 06 , 2012 rev. 1.50 95 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro prm0 register ht67f40 bit 7 6 5 4 3 2 1 0 name c1xps1 c1xps0 c0xps1 c0xps0 simps1 simps0 pckps1 pckps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 c1xps1, c1xps0 : c1x pin remapping control 00: c1x on pa5 01: c1x on pe6 10: c1x on pe7 11: undefned bit 5~4 c0xps1, c0xps0 : c0x pin remapping control 00: c0x on pa0 01: c0x on pe2 10: c0x on pe3 11: undefned bit 3~2 simps1, simps0 : sim pin remapping control 00: sdo on pc1; sdi/sda on pc0; sck/scl on pa7; scs on pa6 01: sdo on pc5; sdi/sda on pc4; sck/scl on pc3; scs on pc2 10: undefned 11: undefned bit 1~0 pckps1, pckps0 : pck and pintb pin remapping control 00: pck on pa5; pintb on pa4 01: pck on pc1; pintb on pc0 10: undefned 11: undefned prm0 register HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name c1xps1 c1xps0 c0xps1 c0xps0 simps1 simps0 pckps1 pckps0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 c1xps1, c1xps0 : c1x pin remapping control 00: c1x on pa5 01: c1x on pe6 10: c1x on pe7 11: undefned bit 5~4 c0xps1, c0xps0 : c0x pin remapping control 00: c0x on pa0 01: c0x on pe2 10: c0x on pe3 11: undefned bit 3~2 simps1, simps0 : sim pin remapping control 00: sdo on pc1; sdi/sda on pc0; sck/scl on pa7; scs on pa6 01: sdo on pc5; sdi/sda on pc4; sck/scl on pc3; scs on pc2 10: sdo on pg5; sdi/sda on pg4; sck/scl on pg3; scs on pg2 11: undefned bit 1~0 pckps1, pckps0 : pck and pintb pin remapping control 00: pck on pa5; pintb on pa4 01: pck on pc1; pintb on pc0 10: pck on pg1; pintb on pg0 11: undefned ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 94 march 06 , 2012 rev. 1.50 95 march 06 , 2012 prm1 register ht67f30 bit 7 6 5 4 3 2 1 0 name tck1ps tck0ps int1ps int0ps tp1b1ps tp1b0ps r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as 0 bit 6 tck1ps : tck1 pin remapping control 0: tck1 on pa4 1: tck1 on pe1 bit 5 tck0ps : tck0 pin remapping control 0: tck0 on pa2 1: tck0 on pe0 bit 4 unimplemented, read as 0 bit 3 int1ps : int1b pin remapping control 0: int1b on pa4 1: int1b on pe5 bit 2 int0ps : int0b pin remapping control 0: int0b on pa3 1: int0b on pe4 bit 1 tp1b1ps : tp1b_1 pin remapping control 0: tp1b_1 on pc1 1: tp1b_1 on pd4 bit 0 tp1b0ps : tp1b_0 pin remapping control 0: tp1b_0 on pc0 1: tp1b_0 on pd3 ht67f40/HT67F50 bit 7 6 5 4 3 2 1 0 name tck2ps tck1ps tck0ps int1ps int0ps tp1b1ps tp1b0ps r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 tck2ps : tck2 pin remapping control 0: tck2 on pc2 1: tck2 on pe2 bit 6 tck1ps : tck1 pin remapping control 0: tck1 on pa4 1: tck1 on pe1 bit 5 tck0ps : tck0 pin remapping control 0: tck0 on pa2 1: tck0 on pe0 bit 4 unimplemented, read as 0 bit 3 int1ps : int1b pin remapping control 0: int1b on pa4 1: int1b on pe5 bit 2 int0ps : int0b pin remapping control 0: int0b on pa3 1: int0b on pe4 bit 1 tp1b1ps : tp1b_1 pin remapping control 0: tp1b_1 on pc1 1: tp1b_1 on pd4 bit 0 tp1b0ps : tp1b_0 pin remapping control 0: tp1b_0 on pc0 1: tp1b_0 on pd3 rev. 1.50 96 march 06 , 2012 rev. 1.50 97 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro prm1 register ht67f60 bit 7 6 5 4 3 2 1 0 name tck2ps tck1ps tck0ps int2ps int1ps int0ps tp1b1ps tp1b0ps r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tck2ps : tck2 pin remapping control 0: tck2 on pc2 1: tck2 on pe2 bit 6 tck1ps : tck1 pin remapping control 0: tck1 on pa4 1: tck1 on pe1 bit 5 tck0ps : tck0 pin remapping control 0: tck0 on pa2 1: tck0 on pe0 bit 4 int2ps : int2 pin remapping control 0: int2 on pc4 1: int2 on pe6 bit 3 int1ps : int1b pin remapping control 0: int1b on pa4 1: int1b on pe5 bit 2 int0ps : int0b pin remapping control 0: int0b on pa3 1: int0b on pe4 bit 1 tp1b1ps : tp1b_1 pin remapping control 0: tp1b_1 on pc1 1: tp1b_1 on pd4 bit 0 tp1b0ps : tp1b_0 pin remapping control 0: tp1b_0 on pc0 1: tp1b_0 on pd3 prm2 register ht67f30 bit 7 6 5 4 3 2 1 0 name tp1aps tp01ps tp00ps r/w r/w r/w r/w por 0 0 0 bit 7~3 unimplemented, read as 0 bit 2 tp1aps : tp1a pin remapping control 0: tp1a on pa1 1: tp1a on pd2 bit 1 tp01ps : tp0_1 pin remapping control 0: tp0_1 on pa7 1: tp0_1 on pd1 bit 0 tp00ps : tp0_0 pin remapping control 0: tp0_0 on pa0 1: tp0_0 on pd0 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 96 march 06 , 2012 rev. 1.50 97 march 06 , 2012 ht67f40 bit 7 6 5 4 3 2 1 0 name tp21ps tp20ps tp1b2ps tp1aps tp01ps tp00ps r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7~6 unimp lemented, read as 0 bit 5 tp21ps : tp2_1 pin remapping control 0: tp2_1 on pc4 1: tp2_1 on pd7 bit 4 tp20ps : tp2_0 pin remapping control 0: tp2_0 on pc3 1: tp2_0 on pd6 bit 3 tp1b2ps : tp1b_2 pin remapping control 0: tp1b_2 on pc5 1: tp1b_2 on pd5 bit 2 tp1aps : tp1a pin remapping control 0: tp1a on pa1 1: tp1a on pd2 bit 1 tp01ps : tp0_1 pin remapping control 0: tp0_1 on pc5 1: tp0_1 on pd1 bit 0 tp00ps : tp0_0 pin remapping control 0: tp0_0 on pa0 1: tp0_0 on pd0 HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name tp31ps tp30ps tp21ps tp20ps tp1b2ps tp1aps tp01ps tp00ps r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tp31ps : tp3_1 pin remapping control 0: tp3_1 on pg0 1: tp3_1 on pf1 bit 6 tp30ps : tp3_0 pin remapping control 0: tp3_0 on pg3 1: tp3_0 on pf0 bit 5 tp21ps : tp2_1 pin remapping control 0: tp2_1 on pc4 1: tp2_1 on pd7 bit 4 tp20ps : tp2_0 pin remapping control 0: tp2_0 on pc3 1: tp2_0 on pd6 bit 3 tp1b2ps : tp1b_2 pin remapping control 0: tp1b_2 on pc5 1: tp1b_2 on pd5 bit 2 tp1aps : tp1a pin remapping control 0: tp1a on pa1 1: tp1a on pd2 bit 1 tp01ps : tp0_1 pin remapping control 0: tp0_1 on pc5 1: tp0_1 on pd1 bit 0 tp00ps : tp0_0 pin remapping control 0: tp0_0 on pa0 1: tp0_0 on pd0 rev. 1.50 98 march 06 , 2012 rev. 1.50 99 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro i/o pin structures the accompanying diagrams illustrate the internal structures of some generic i/o pin types. as the exact logical construction of the i/o pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the i/o pins. the wide range of pin-shared structures does not permit all types to be shown. programming considerations within the user program, one of the frst things to consider is port initialisation. after a reset, all of the i/o data and port control registers will be set high. this means that all i/o pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. if the port control registers, pac~phc, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, pa~ph, are frst programmed. selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the set [m].i and clr [m].i instructions. note that when using these bit control instructions, a read-modify-write operation takes place. the microcontroller must frst read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. port a has the additional capability of providing wake-up functions. when the device is in the sleep or idle mode, various methods are available to wake the device up. one of these is a high to low transition of any of the port a pins. single or multiple pins on port a can be setup to have this function. ??? ?? ? ? ? generic input/output structure ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 98 march 06 , 2012 rev. 1.50 99 march 06 , 2012 timer modules C tm one of the most fundamental functions in any microcontroller device is the ability to control and measure time. to implement time related functions each device includes several timer modules, abbreviated to the name tm. the tms are multi-purpose timing units and serve to provide operations such as timer/counter, input capture, compare match output and single pulse output as well as being the functional unit for the generation of pwm signals. each of the tms has either two or three individual interrupts. the addition of input and output pins for each tm ensures that users are provided with timing units with a wide and fexible range of features. the common features of the different tm types are described here with more detailed information provided in the individual compact, standard and enhanced tm sections. introduction the devices contain from two to four tms depending upon which device is selected with each tm having a reference name of tm0, tm1, tm2 and tm3. each individual tm can be categorised as a certain type, namely compact type tm, standard type tm or enhanced type tm. although similar in nature, the different tm types vary in their feature complexity. the common features to all of the compact, standard and enhanced tms will be described in this section, the detailed operation regarding each of the tm types will be described in separate sections. the main features and differences between the three types of tms are summarised in the accompanying table. function ctm stm etm timer/counter i/p capture compare match output pwm channels 1 1 2 single pulse output 1 2 pwm alignment edge edge edge & centre pwm adjustment period & duty duty or period duty or period duty or period tm function summary each device in the series contains a specifc number of either compact type, standard type and enhanced type tm units which are shown in the table together with their individual reference name, tm0~tm3. device tm0 tm1 tm2 tm3 ht67f30 10-bit ctm 10-bit etm ht67f40 10-bit ctm 10-bit etm 16-bit stm HT67F50 10-bit ctm 10-bit etm 16-bit stm 10-bit ctm ht67f60 10-bit ctm 10-bit etm 16-bit stm 10-bit ctm tm name/type reference rev. 1.50 100 march 06 , 2012 rev. 1.50 101 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro tm operation the three different types of tm offer a diverse range of functions, from simple timing operations to pwm signal generation. the key to understanding how the tm operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. when the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a tm interrupt signal will be generated which can clear the counter and perhaps also change the condition of the tm output pin. the internal tm counter is driven by a user selectable clock source, which can be an internal clock or an external pin. tm clock source the clock source which drives the main counter in each tm can originate from various sources. the selection of the required clock source is implemented using the tnck2~tnck0 bits in the tm control registers. the clock source can be a ratio of either the system clock f sys or the internal high clock f h , the f tbc clock source or the external tckn pin. note that setting these bits to the value 101 will select a reserved clock input, in effect disconnecting the tm clock source. the tckn pin clock source is used to allow an external signal to drive the tm as an external clock source or for event counting. tm interrupts the compact and standard type tms each have two internal interrupts, one for each of the internal comparator a or comparator p, which generate a tm interrupt when a compare match condition occurs. as the enhanced type tm has three internal comparators and comparator a or comparator b or comparator p compare match functions, it consequently has three internal interrupts. when a tm interrupt is generated it can be used to clear the counter and also to change the state of the tm output pin. tm external pins each of the tms, irrespective of what type, has one tm input pin, with the label tckn. the tm input pin, is essentially a clock source for the tm and is selected using the tnck2~tnck0 bits in the tmnc0 register. this external tm input pin allows an external clock source to drive the internal tm. this external tm input pin is shared with other functions but will be connected to the internal tm if selected using the tnck2~tnck0 bits. the tm input pin can be chosen to have either a rising or falling active edge. the tms each have one or more output pins with the label tpn. when the tm is in the compare match output mode, these pins can be controlled by the tm to switch to a high or low level or to toggle when a compare match situation occurs. the external tpn output pin is also the pin where the tm generates the pwm output waveform. as the tm output pins are pin-shared with other function, the tm output function must first be setup using registers. a single bit in one of the registers determines if its associated pin is to be used as an external tm output pin or if it is to have another function. the number of output pins for each tm type and device is different, the details are provided in the accompanying table. all tm output pin names have a _n suffx. pin names that include a _1 or _2 suffx indicate that they are from a tm with multiple output pins. this allows the tm to generate a complimentary output pair, selected using the i/o register data bits. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 100 march 06 , 2012 rev. 1.50 101 march 06 , 2012 device ctm stm etm registers ht67f30 tp0_0, tp0_1 tp1a, tp1b_0, tp1b_1 tmpc0 ht67f40 tp0_0, tp0_1 tp2_0, tp2_1 tp1a, tp1b_0, tp1b_1, tp1b_2 tmpc0, tmpc1 HT67F50 tp0_0, tp0_1 tp3_0, tp3_1 tp2_0, tp2_1 tp1a, tp1b_0, tp1b_1, tp1b_2 tmpc0, tmpc1 ht67f60 tp0_0, tp0_1 tp3_0, tp3_1 tp2_0, tp2_1 tp1a, tp1b_0, tp1b_1, tp1b_2 tmpc0, tmpc1 tm output pins tm input/output pin control registers selecting to have a tm input/output or whether to retain its other shared function, is implemented using one or two registers, with a single bit in each register corresponding to a tm input/output pin. setting the bit high will setup the corresponding pin as a tm input/output, if reset to zero the pin will retain its original other function. registers device bit 7 6 5 4 3 2 1 0 tmpc0 ht67f30 t1acp0 t1bcp1 t1bcp0 t0cp1 t0cp0 tmpc0 ht67f40 HT67F50 ht67f60 t1acp0 t1bcp2 t1bcp1 t1bcp0 t0cp1 t0cp0 tmpc1 ht67f40 t2cp1 t2cp0 tmpc1 HT67F50 ht67f60 t3cp1 t3cp0 t2cp1 t2cp0 tm input/output pin control registers list rev. 1.50 102 march 06 , 2012 rev. 1.50 103 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ht67f30 tm function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 102 march 06 , 2012 rev. 1.50 103 march 06 , 2012 ht67f40 tm0 & tm2 function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input. rev. 1.50 104 march 06 , 2012 rev. 1.50 105 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ht67f40 tm1 function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 104 march 06 , 2012 rev. 1.50 105 march 06 , 2012 HT67F50 and ht67f60 tm0, tm2, tm3 function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input. rev. 1.50 106 march 06 , 2012 rev. 1.50 107 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro HT67F50 and ht67f60 tm1 function pin control block diagram note: (1) the i/o register data bits shown are used for tm output inversion control. (2) in the capture input mode, the tm pin control register must never enable more than one tm input. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 106 march 06 , 2012 rev. 1.50 107 march 06 , 2012 tmpc0 register ht67f30 bit 7 6 5 4 3 2 1 0 name t1acp0 t1bcp1 t1bcp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w por 1 0 1 0 1 bit 7 t1acp0 : tp1a pin control 0: disable 1: enable bit 6 unimplemented, read as "0" bit 5 t1bcp1 : tp1b_1 pin control 0: disable 1: enable bit 4 t1bcp0 : tp1b_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as "0" bit 1 t0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name t1acp0 t1bcp2 t1bcp1 t1bcp0 t0cp1 t0cp0 r/w r/w r/w r/w r/w r/w r/w por 1 0 0 1 0 1 bit 7 t1acp0 : tp1a pin control 0: disable 1: enable bit 6 t1bcp2 : tp1b_2 pin control 0: disable 1: enable bit 5 t1bcp1 : tp1b_1 pin control 0: disable 1: enable bit 4 t1bcp0 : tp1b_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as "0" bit 1 t0cp1 : tp0_1 pin control 0: disable 1: enable bit 0 t0cp0 : tp0_0 pin control 0: disable 1: enable rev. 1.50 108 march 06 , 2012 rev. 1.50 109 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro tmpc1 register ht67f40 bit 7 6 5 4 3 2 1 0 name t2cp1 t2cp0 r/w r/w r/w por 0 1 bit 7~2 unimplemented, read as "0" bit 1 t2cp1 : tp2_1 pin control 0: disable 1: enable bit 0 t2cp0 : tp2_0 pin control 0: disable 1: enable HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name t3cp1 t3cp0 t2cp1 t2cp0 r/w r/w r/w r/w r/w por 0 1 0 1 bit 7~6 unimplemented, read as "0" bit 5 t3cp1 : tp3_1 pin control 0: disable 1: enable bit 4 t3cp0 : tp3_0 pin control 0: disable 1: enable bit 3~2 unimplemented, read as "0" bit 1 t2cp1 : tp2_1 pin control 0: disable 1: enable bit 0 t2cp0 : tp2_0 pin control 0: disable 1: enable ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 108 march 06 , 2012 rev. 1.50 109 march 06 , 2012 programming considerations the tm counter registers and the capture/compare ccra and ccrb registers, being either 10-bit or 16-bit, all have a low and high byte structure. the high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specifc way. the important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. data bus 8 - bit buffer tmxdh tmxdl tmxbh tmxbl tmxah tmxal tm counter register ( read only ) tm ccra register ( read / write ) tm ccrb register ( read / write ) the following steps show the read and write procedures: writing data to ccrb or ccra ? step 1. write data to low byte tmxal or tmxbl C note that here data is only written to the 8-bit buffer. ? step 2. write data to high byte tmxah or tmxbh C here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the low byte registers. reading data from the counter registers and ccrb or ccra ? step 1. read data from the high byte tmxdh, tmxah or tmxbh C here data is read directly from the high byte registers and simultaneously data is latched from the low byte register into the 8-bit buffer. ? step 2. read data from the low byte tmxdl, tmxal or tmxbl C this step reads data from the 8-bit buffer. as the ccra and ccrb registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specifc way described above, it is recommended to use the mov instruction to access the ccra and ccrb low byte registers, named tmxal and tmxbl, using the following access procedures. accessing the ccra or ccrb low byte registers without following these access procedures will result in unpredictable values. rev. 1.50 110 march 06 , 2012 rev. 1.50 111 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro compact type tm although the simplest form of the three tm types, the compact tm type still contains three operating modes, which are compare match output, timer/event counter and pwm output modes. the compact tm can also be controlled with an external input pin and can drive one or two external output pins. these two external output pins can be the same signal or the inverse signal. tm name tm no. tm input pin tm output pin ht67f30 10-bit ctm 0 tck0 tp0_0, tp0_1 ht67f40 10-bit ctm 0 tck0 tp0_0, tp0_1 HT67F50 10-bit ctm 0, 3 tck0, tck3 tp0_0, tp0_1; tp3_0, tp3_1 ht67f60 10-bit ctm 0, 3 tck0, tck3 tp0_0, tp0_1; tp3_0, tp3_1 compact tm operation at its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp is three bits wide whose value is compared with the highest three bits in the counter while the ccra is the ten bits and therefore compares with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the compact type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - - ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? compact type tm block diagram ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 110 march 06 , 2012 rev. 1.50 111 march 06 , 2012 compact type tm register description overall operation of the compact tm is controlled using six registers. a read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tmnc0 tnpau tnck2 tnck1 tnck0 tnon tnrp2 tnrp1 tnrp0 tmnc1 tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr tmndl d7 d6 d5 d4 d3 d2 d1 d0 tmndh d9 d8 tmnal d7 d6 d5 d4 d3 d2 d1 d0 tmnah d9 d8 compact tm register list (n=0 or 3) tmndl register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tmndl : tmn counter low byte register bit 7 ~ bit 0 tmn 10-bit counter bit 7 ~ bit 0 tmndh register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmndh : tmn counter high byte register bit 1 ~ bit 0 tmn 10-bit counter bit 9 ~ bit 8 tmnal register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tmnal : tmn ccra low byte register bit 7 ~ bit 0 tmn 10-bit ccra bit 7 ~ bit 0 tmnah register bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tmnah : tmn ccra high byte register bit 1 ~ bit 0 tmn 10-bit ccra bit 9 ~ bit 8 rev. 1.50 112 march 06 , 2012 rev. 1.50 113 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro tmnc0 register bit 7 6 5 4 3 2 1 0 name tnpau tnck2 tnck1 tnck0 tnon tnrp2 tnrp1 tnrp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 tnpau : tmn counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 tnck2~tnck0 : select tmn counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tckn rising edge clock 111: tckn falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 tnon : tmn counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the tnoc bit, when the tnon bit changes from low to high. bit 2~0 tnrp2~tnrp0 : tmn ccrp 3-bit register, compared with the tmn counter bit 9~bit 7 comparator p match period 000: 1024 tmn clocks 001: 128 tmn clocks 010: 256 tmn clocks 011: 384 tmn clocks 100: 512 tmn clocks 101: 640 tmn clocks 110: 768 tmn clocks 111: 896 tmn clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter's highest three bits. the result of this comparison can be selected to clear the internal counter if the tncclr bit is set to zero. setting the tncclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 112 march 06 , 2012 rev. 1.50 113 march 06 , 2012 tmnc1 register bit 7 6 5 4 3 2 1 0 name tnm1 tnm0 tnio1 tnio0 tnoc tnpol tndpx tncclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 tnm1~tnm0 : select tmn operating mode 00: compare match output mode 01: undefned 10: pwm mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the tnm1 and tnm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 tnio1~tnio0 : select tpn_0, tpn_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: undefned timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the tnoc bit in the tmnc1 register. note that the output level requested by the tnio1 and tnio0 bits must be different from the initial value setup using the tnoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the tnon bit from low to high. in the pwm mode, the tnio1 and tnio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the tnio1 and tnio0 bits only after the tmn has been switched off. unpredictable pwm outputs will occur if the tnio1 and tnio0 bits are changed when the tm is running. bit 3 tnoc : tpn_0, tpn_1 output control bit compare match output mode 0: initial low 1: initial high pwm mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode. rev. 1.50 114 march 06 , 2012 rev. 1.50 115 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 tnpol : tpn_0, tpn_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tpn_0 or tpn_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 tndpx : tmn pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 tncclr : select tmn counter clear condition 0: tmn comparatror p match 1: tmn comparatror a match this bit is used to select the method which clears the counter. remember that the compact tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the tncclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the tncclr bit is not used in the pwm mode. compact type tm operating modes the compact type tm can operate in one of three operating modes, compare match output mode, pwm mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare match output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both tnaf and tnpf interrupt request fags for the comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. if the ccra bits are all zero, the counter will overfow when its reaches its maximum 10-bit, 3ff hex, value, however here the tnaf interrupt request fag will not be generated. as the name of the mode suggests, after a comparison is made, the tm output pin will change state. the tm output pin condition however only changes state when an tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 114 march 06 , 2012 rev. 1.50 115 march 06 , 2012 tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. counter value 0 x 3 ff ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin time ccrp = 0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0 ; tnm [ 1 : 0 ] = 00 output pin set to initial level low if tnoc = 0 output toggle with tnaf flag note tnio [ 1 : 0 ] = 10 active high output select here tnio [ 1 : 0 ] = 11 toggle output select output not affected by tnaf flag . remains high until reset by tnon bit output pin reset to initial value output controlled by other pin - shared function output inverts when tnpol is high compare match output mode tncclr = 0 note: 1. with tncclr=0, a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge rev. 1.50 116 march 06 , 2012 rev. 1.50 117 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro counter value 0 x 3 ff ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin time ccra = 0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1 ; tnm [ 1 : 0 ] = 00 output pin set to initial level low if tnoc = 0 output toggle with tnaf flag note tnio [ 1 : 0 ] = 10 active high output select here tnio [ 1 : 0 ] = 11 toggle output select output not affected by tnaf flag . remains high until reset by tnon bit output pin reset to initial value output controlled by other pin - shared function output inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change compare match output mode tncclr = 1 note: 1. with tncclr=1, a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect on the pwm operation. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 116 march 06 , 2012 rev. 1.50 117 march 06 , 2012 ctm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 16mhz, tm clock source is f sys /4, ccrp = 100b and ccra = 128, the ctm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125 khz, duty = 128/512 = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. ctm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the ccrp register value. counter value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc = 1 ) time counter cleared by ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0 ; tnm [ 1 : 0 ] = 10 pwm duty cycle set by ccra pwm resumes operation output controlled by other pin - shared function output inverts when tnpol = 1 pwm period set by ccrp tm o / p pin ( tnoc = 0 ) pwm mode tndpx = 0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation rev. 1.50 118 march 06 , 2012 rev. 1.50 119 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro counter value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc = 1 ) time counter cleared by ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1 ; tnm [ 1 : 0 ] = 10 pwm duty cycle set by ccrp pwm resumes operation output controlled by other pin - shared function output inverts when tnpol = 1 pwm period set by ccra tm o / p pin ( tnoc = 0 ) pwm mode tndpx = 1 note: 1. here tndpx = 1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation standard type tm C stm the standard type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. the standard tm can also be controlled with an external input pin and can drive one or two external output pins. ctm name tm no. tm input pin tm output pin ht67f30 ht67f40 16-bit stm 2 tck2 tp2_0, tp2_1 HT67F50 16-bit stm 2 tck2 tp2_0, tp2_1 ht67f60 16-bit stm 2 tck2 tp2_0, tp2_1 standard tm operation there are two sizes of standard tms, one is 10-bits wide and the other is 16-bits wide. at the core is a 10 or 16-bit count-up counter which is driven by a user selectable internal or external clock source. there are also two internal comparators with the names, comparator a and comparator p. these comparators will compare the value in the counter with ccrp and ccra registers. the ccrp comparator is 3 or 8-bits wide whose value is compared the with highest 3 or 8 bits in the counter while the ccra is the ten or sixteen bits and therefore compares all counter bits. the only way of changing the value of the 10 or 16-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the standard type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. all operating setup conditions are selected using relevant internal registers. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 118 march 06 , 2012 rev. 1.50 119 march 06 , 2012 standard type tm register description overall operation of the standard tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10 or 16-bit value, while a read/write register pair exists to store the internal 10 or 16-bit ccra value. the remaining two registers are control registers which setup the different operating and control modes as well as the three or eight ccrp bits. ? ? ? ? ? ?? ? ? ? ? ? ? ? - ? ? ? - ? ? ? - ? ? ? ? ? ??? ?? ? - ? - ? - ? - ? ? ? ? ? ? ? ? ? ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? standard type tm block diagram name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm2c0 t2pau t2ck2 t2ck1 t2ck0 t2on tm2c1 t2m1 t2m0 t2io1 t2io0 t2oc t2pol t2dpx t2cclr tm2dl d7 d6 d5 d4 d3 d2 d1 d0 tm2dh d15 d14 d13 d12 d11 d10 d9 d8 tm2al d7 d6 d5 d4 d3 d2 d1 d0 tm2ah d15 d14 d13 d12 d11 d10 d9 d8 tm2rp d7 d6 d5 d4 d3 d2 d1 d0 16-bit standard tm register list (for ht67f40/HT67F50/ht67f60) rev. 1.50 120 march 06 , 2012 rev. 1.50 121 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro 16-bit standard tm register list - ht67f40/HT67F50/ht67f60 tm2c0 register - 16-bit stm bit 7 6 5 4 3 2 1 0 name t2pau t2ck2 t2ck1 t2ck0 t2on r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 bit 7 t2pau : tm2 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t2ck2, t2ck1, t2ck0 : select tm2 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tck2 rising edge clock 111: tck2 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t2on : tm2 counter on/off control 0: off 1: on this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t2oc bit, when the t2on bit changes from low to high. bit 2~0 unimplemented, read as "0" ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 120 march 06 , 2012 rev. 1.50 121 march 06 , 2012 tm2c1 register - 16-bit stm bit 7 6 5 4 3 2 1 0 name t2m1 t2m0 t2io1 t2io0 t2oc t2pol t2dpx t2cclr r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 t2m1~t2m0 : select tm2 operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t2m1 and t2m0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t2io1~t2io0 : select tp2_0, tp2_1 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/ single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp2_0, tp2_1 01: input capture at falling edge of tp2_0, tp2_1 10: input capture at falling/rising edge of tp2_0, tp2_1 11: input capture disabled timer/counter mode: unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t2io1 and t2io0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t2oc bit in the tm2c1 register. note that the output level requested by the t2io1 and t2io0 bits must be different from the initial value setup using the t2oc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t2on bit from low to high. in the pwm mode, the t1io1 and t1io0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the values of the t1io1 and t1io0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1io1 and t1io0 bits are changed when the tm is running. bit 3 t2oc : tp2_0, tp2_1 output control bit compare match output mode 0: initial low 1: initial high rev. 1.50 122 march 06 , 2012 rev. 1.50 123 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t2pol : tp2_0, tp2_1 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp2_0 or tp2_1 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t2dpx : tm2 pwm period/duty control 0: ccrp - period; ccra - duty 1: ccrp - duty; ccra - period this bit, determines which of the ccra and ccrp registers are used for period and duty control of the pwm waveform. bit 0 t2cclr : select tm2 counter clear condition 0: tm2 comparator p match 1: tm2 comparator a match this bit is used to select the method which clears the counter. remember that the standard tm contains two comparators, comparator a and comparator p, either of which can be selected to clear the internal counter. with the t2cclr bit set high, the counter will be cleared when a compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overflow. a counter overflow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the pwm, single pulse or input capture mode. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 122 march 06 , 2012 rev. 1.50 123 march 06 , 2012 tm2dl register - 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm2dl : tm2 counter low byte register bit 7~bit 0 tm2 16-bit counter bit 7~bit 0 tm2dh register - 16-bit stm bit 7 6 5 4 3 2 1 0 name d15 d14 d13 d12 d11 d10 d9 d8 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm2dh : tm2 counter high byte register bit 7~bit 0 tm2 16-bit counter bit 15~bit 8 tm2al register - 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2al : tm2 ccra low byte register bit 7~bit 0 tm2 16-bit ccra bit 7~bit 0 tm2ah register - 16-bit stm bit 7 6 5 4 3 2 1 0 name d15 d14 d13 d12 d11 d10 d9 d8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2ah : tm2 ccra high byte register bit 7~bit 0 tm2 16-bit ccra bit 15~bit 8 tm2rp register - 16-bit stm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm2rp : tm2 ccrp register bit 7 ~ bit 0 tm2 ccrp 8-bit register, compared with the tm2 counter bit 15 ~ bit 8. comparator p match period 0: 65536 tm2 clocks 1~255: 256 x (1~255) tm2 clocks these eight bits are used to setup the value on the internal ccrp 8-bit register, which are then compared with the internal counter's highest eight bits. the result of this comparison can be selected to clear the internal counter if the t2cclr bit is set to zero. setting the t2cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. rev. 1.50 124 march 06 , 2012 rev. 1.50 125 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro standard type tm operating modes the standard type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnm1 and tnm0 bits in the tmnc1 register. compare output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register, should be set to 00 respectively. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match from comparator p, the other is when the ccrp bits are all zero which allows the counter to overflow. here both tnaf and tnpf interrupt request flags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. in the compare match output mode, the ccra can not be set to "0". as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an tnaf interrupt request fag is generated after a compare match occurs from comparator a. the tnpf interrupt request flag, generated from a compare match occurs from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state are determined by the condition of the tnio1 and tnio0 bits in the tmnc1 register. the tm output pin can be selected using the tnio1 and tnio0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnoc bit. note that if the tnio1 and tnio0 bits are zero then no pin change will take place. 10-bit stm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 duty ccra if f sys = 16mhz, tm clock source select f sys /4, ccrp = 100b and ccra = 128, the stm pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125khz, duty = 128/512 = 25% if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 10-bit stm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period ccra duty 128 256 384 512 640 768 896 1024 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the ccrp register value. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 124 march 06 , 2012 rev. 1.50 125 march 06 , 2012 16-bit stm, pwm mode, edge-aligned mode, t0dpx=0 ccrp 1~255 000b period ccrp x 256 65536 duty ccra if f sys = 16mhz, tm clock source select f sys /4, ccrp = 2 and ccra = 128, the stm pwm output frequency = (f sys /4) / (2 x 256) = f sys /2048 = 7.8125khz, duty = 128 / (2 x 256) = 25%. if the duty value defned by the ccra register is equal to or greater than the period value, then the pwm output duty is 100%. 16-bit stm, pwm mode, edge-aligned mode, t0dpx=1 ccrp 1~255 000b period ccra duty ccrp x 256 65536 the pwm output period is determined by the ccra register value together with the tm clock while the pwm duty cycle is defned by the (ccrp x 256) except when the ccrp value is equal to 000b. counter value 0 x 3 ff ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin time ccrp = 0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0 ; tnm [ 1 : 0 ] = 00 output pin set to initial level low if tnoc = 0 output toggle with tnaf flag note tnio [ 1 : 0 ] = 10 active high output select here tnio [ 1 : 0 ] = 11 toggle output select output not affected by tnaf flag . remains high until reset by tnon bit output pin reset to initial value output controlled by other pin - shared function output inverts when tnpol is high compare match output mode tncclr = 0 note: 1. with tncclr=0 a comparator p match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to itsinitial state by a tnon bit rising edge rev. 1.50 126 march 06 , 2012 rev. 1.50 127 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro counter value 0 x 3 ff ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin time ccra = 0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1 ; tnm [ 1 : 0 ] = 00 output pin set to initial level low if tnoc = 0 output toggle with tnaf flag note tnio [ 1 : 0 ] = 10 active high output select here tnio [ 1 : 0 ] = 11 toggle output select output not affected by tnaf flag . remains high until reset by tnon bit output pin reset to initial value output controlled by other pin - shared function output inverts when tnpol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change compare match output mode tncclr = 1 note: 1. with tncclr=1 a comparator a match will clear the counter 2. the tm output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge 4. a tnpf fag is not generated when tncclr=1 timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 126 march 06 , 2012 rev. 1.50 127 march 06 , 2012 an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. counter value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc = 1 ) time counter cleared by ccrp pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 0 ; tnm [ 1 : 0 ] = 10 pwm duty cycle set by ccra pwm resumes operation output controlled by other pin - shared function output inverts when tnpol = 1 pwm period set by ccrp tm o / p pin ( tnoc = 0 ) pwm mode tndpx = 0 note: 1. here tndpx=0 C counter cleared by ccrp 2. a counter clear sets the pwm period 3. the internal pwm function continues running even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation rev. 1.50 128 march 06 , 2012 rev. 1.50 129 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro counter value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc = 1 ) time counter cleared by ccra pause resume counter stop if tnon bit low counter reset when tnon returns high tndpx = 1 ; tnm [ 1 : 0 ] = 10 pwm duty cycle set by ccrp pwm resumes operation output controlled by other pin - shared function output inverts when tnpol = 1 pwm period set by ccra tm o / p pin ( tnoc = 0 ) pwm mode tndpx = 1 note: 1. here tndpx=1 C counter cleared by ccra 2. a counter clear sets the pwm period 3. the internal pwm function continues even when tnio [1:0] = 00 or 01 4. the tncclr bit has no infuence on pwm operation single pulse mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. ? ? ? ? ? ? ? ? ? ?? single pulse generation ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 128 march 06 , 2012 rev. 1.50 129 march 06 , 2012 counter value ccrp ccra tnon tnpau tnpol ccrp int . flag tnpf ccra int . flag tnaf tm o / p pin ( tnoc = 1 ) time counter stopped by ccra pause resume counter stops by software counter reset when tnon returns high tnm [ 1 : 0 ] = 10 ; tnio [ 1 : 0 ] = 11 pulse width set by ccra output inverts when tnpol = 1 no ccrp interrupts generated tm o / p pin ( tnoc = 0 ) tckn pin software trigger cleared by ccra match tckn pin trigger auto . set by tckn pin software trigger software clear software trigger software trigger single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit hight 5. in the single pulse mode, tnio [1:0] must be set to 11 and can not be changed. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge. in this way the ccra value can be used to control the pulse width. a compare match from comparator a will also generate a tm interrupt. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr and tndpx bits are not used in this mode. capture input mode to select this mode bits tnm1 and tnm0 in the tmnc1 register should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpn_0 or tpn_1 pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnio1 and tnio0 bits in the tmnc1 register. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpn_0 or tpn_1 pin the present value in the counter will be latched into the ccra registers and a tm interrupt generated. irrespective of what events occur on the tpn_0 or tpn_1 pin the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overflow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnio1 and tnio0 bits can select the active trigger edge on the tpn_0 or tpn_1 pin to be a rising edge, falling edge or both edge types. if the tnio1 and tnio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpn_0 or tpn_1 pin, however it must be noted that the counter will continue to run. rev. 1.50 130 march 06 , 2012 rev. 1.50 131 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro as the tpn_0 or tpn_1 pin is pin shared with other functions, care must be taken if the tm is in the input capture mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr and tndpx bits are not used in this mode. counter value yy ccrp tnon tnpau ccrp int . flag tnpf ccra int . flag tnaf ccra value time counter cleared by ccrp pause resume counter reset tnm [ 1 : 0 ] = 01 tm capture pin tpn _ x xx counter stop tnio [ 1 : 0 ] value xx yy xx yy active edge active edge active edge 00 ? rising edge 01 ? falling edge 10 ? both edges 11 ? disable capture capture input mode note: 1. tnm [1:0] = 01 and active edge set by the tnio [1:0] bits 2. a tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnoc and tnpol bits are not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 130 march 06 , 2012 rev. 1.50 131 march 06 , 2012 enhanced type tm C etm the enhanced type tm contains fve operating modes, which are compare match output, timer/ event counter, capture input, single pulse output and pwm output modes. the enhanced tm can also be controlled with an external input pin and can drive three or four external output pins. ctm name tm no. tm input pin tm output pin ht67f30 10-bit etm 1 tck1 tp1a; tp1b_0, tp1b_1 ht67f40 10-bit etm 1 tck1 tp1a, tp1b_0, tp1b_1, tp1b_2 HT67F50 10-bit etm 1 tck1 tp1a, tp1b_0, tp1b_1, tp1b_2 ht67f60 10-bit etm 1 tck1 tp1a, tp1b_0, tp1b_1, tp1b_2 enhanced tm operation at its core is a 10-bit count-up/count-down counter which is driven by a user selectable internal or external clock source. there are three internal comparators with the names, comparator a, comparator b and comparator p. these comparators will compare the value in the counter with the ccra, ccrb and ccrp registers. the ccrp comparator is 3-bits wide whose value is compared with the highest 3-bits in the counter while ccra and ccrb are 10-bits wide and therefore compared with all counter bits. the only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the tnon bit from low to high. the counter will also be cleared automatically by a counter overfow or a compare match with one of its associated comparators. when these conditions occur, a tm interrupt signal will also usually be generated. the enhanced type tm can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control output pins. all operating setup conditions are selected using relevant internal registers. ? ? ? ?? ? ? ? - ? ? - ? - ? ? ??? ?? ? - ? - ? - ? - ? ? ? ? ? ??? ?? ? ??? ? ? ? ? ? ? ?? ? ? ? ? ?? ? ?? ?? - ? ? - ? ? ? ? ?- ? ?- ? ? ? ? ? ? ? ? ? ? ??? ?? ? - ? - ? ? ? enhanced type tm block diagram rev. 1.50 132 march 06 , 2012 rev. 1.50 133 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro enhanced type tm register description overall operation of the enhanced tm is controlled using a series of registers. a read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit ccra and ccrb value. the remaining three registers are control registers which setup the different operating and control modes as well as the three ccrp bits. name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 tm1c0 t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 tm1c1 t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr tm1c2 t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 tm1dl d7 d6 d5 d4 d3 d2 d1 d0 tm1dh d9 d8 tm1al d7 d6 d5 d4 d3 d2 d1 d0 tm1ah d9 d8 tm1bl d7 d6 d5 d4 d3 d2 d1 d0 tm1bh d9 d8 10-bit enhanced tm register list (if etm is tm1) 10-bit enhanced tm register list - ht67f30/ht67f40/HT67F50/ht67f60 tm1c0 register - 10-bit etm bit 7 6 5 4 3 2 1 0 name t1pau t1ck2 t1ck1 t1ck0 t1on t1rp2 t1rp1 t1rp0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t1pau : tm1 counter pause control 0: run 1: pause the counter can be paused by setting this bit high. clearing the bit to zero restores normal counter operation. when in a pause condition the tm will remain powered up and continue to consume power. the counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. bit 6~4 t1ck2~t1ck0 : select tm1 counter clock 000: f sys /4 001: f sys 010: f h /16 011: f h /64 100: f tbc 101: undefned 110: tck1 rising edge clock 111: tck1 falling edge clock these three bits are used to select the clock source for the tm. selecting the reserved clock input will effectively disable the internal counter. the external pin clock source can be chosen to be active on the rising or falling edge. the clock source f sys is the system clock, while f h and f tbc are other internal clocks, the details of which can be found in the oscillator section. bit 3 t1on : tm1 counter on/off control 0: off 1: on ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 132 march 06 , 2012 rev. 1.50 133 march 06 , 2012 this bit controls the overall on/off function of the tm. setting the bit high enables the counter to run, clearing the bit disables the tm. clearing this bit to zero will stop the counter from counting and turn off the tm which will reduce its power consumption. when the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. if the tm is in the compare match output mode then the tm output pin will be reset to its initial condition, as specifed by the t1oc bit, when the t1on bit changes from low to high. bit 2~0 t1rp2~t1rp0 : tm1 ccrp 3-bit register, compared with the tm1 counter bit 9~bit 7 comparator p match period 000: 1024 tm1 clocks 001: 128 tm1 clocks 010: 256 tm1 clocks 011: 384 tm1 clocks 100: 512 tm1 clocks 101: 640 tm1 clocks 110: 768 tm1 clocks 111: 896 tm1 clocks these three bits are used to setup the value on the internal ccrp 3-bit register, which are then compared with the internal counter highest three bits. the result of this comparison can be selected to clear the internal counter if the t1cclr bit is set to zero. setting the t1cclr bit to zero ensures that a compare match with the ccrp values will reset the internal counter. as the ccrp bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. tm1c1 register - 10-bit etm bit 7 6 5 4 3 2 1 0 name t1am1 t1am0 t1aio1 t1aio0 t1aoc t1apol t1cdn t1cclr r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1am1~t1am0 : select tm1 ccra operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1am1 and t1am0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1aio1~t1aio0 : select tp1a output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/ single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output rev. 1.50 134 march 06 , 2012 rev. 1.50 135 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro capture input mode 00: input capture at rising edge of tp1a 01: input capture at falling edge of tp1a 10: input capture at falling/rising edge of tp1a 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1aoc bit in the tm1c1 register. note that the output level requested by the t1aio1 and t1aio0 bits must be different from the initial value setup using the t1aoc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1aio1 and t1aio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modifed by changing these two bits. it is necessary to change the values of the t1aio1 and t1aio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1aio1 and t1aio0 bits are changed when the tm is running. bit 3 t1aoc : tp1a output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1apol : tp1a output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1a output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1 t1cdn : tm1 counter count up or down fag 0: count up 1: count down bit 0 t1cclr : select tm1 counter clear condition 0: tm1 comparator p match 1: tm1 comparator a match this bit is used to select the method which clears the counter. remember that the enhanced tm contains three comparators, comparator a, comparator b and comparator p, but only comparator a or comparator p can be selected to clear the internal counter. with the t1cclr bit set high, the counter will be cleared when a ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 134 march 06 , 2012 rev. 1.50 135 march 06 , 2012 compare match occurs from the comparator a. when the bit is low, the counter will be cleared when a compare match occurs from the comparator p or with a counter overfow. a counter overfow clearing method can only be implemented if the ccrp bits are all cleared to zero. the t1cclr bit is not used in the single pulse or input capture mode. tm1c2 register - 10-bit etm bit 7 6 5 4 3 2 1 0 name t1bm1 t1bm0 t1bio1 t1bio0 t1boc t1bpol t1pwm1 t1pwm0 r/w r/w r/w r/w r/w r/w r/w r r/w por 0 0 0 0 0 0 0 0 bit 7~6 t1bm1~t1bm0 : select tm1 ccrb operating mode 00: compare match output mode 01: capture input mode 10: pwm mode or single pulse output mode 11: timer/counter mode these bits setup the required operating mode for the tm. to ensure reliable operation the tm should be switched off before any changes are made to the t1bm1 and t1bm0 bits. in the timer/counter mode, the tm output pin control must be disabled. bit 5~4 t1bio1~t1bio0 : select tp1b_0, tp1b_1, tp1b_2 output function compare match output mode 00: no change 01: output low 10: output high 11: toggle output pwm mode/single pulse output mode 00: pwm output inactive state 01: pwm output active state 10: pwm output 11: single pulse output capture input mode 00: input capture at rising edge of tp1b_0, tp1b_1, tp1b_2 01: input capture at falling edge of tp1b_0, tp1b_1, tp1b_2 10: input capture at falling/rising edge of tp1b_0, tp1b_1, tp1b_2 11: input capture disabled timer/counter mode unused these two bits are used to determine how the tm output pin changes state when a certain condition is reached. the function that these bits select depends upon in which mode the tm is running. in the compare match output mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a compare match occurs from the comparator a. the tm output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the comparator a. when the bits are both zero, then no change will take place on the output. the initial value of the tm output pin should be setup using the t1boc bit in the tm1c2 register. note that the output level requested by the t1bio1 and t1bio0 bits must be different from the initial value setup using the t1boc bit otherwise no change will occur on the tm output pin when a compare match occurs. after the tm output pin changes state it can be reset to its initial level by changing the level of the t1on bit from low to high. in the pwm mode, the t1bio1 and t1bio0 bits determine how the tm output pin changes state when a certain compare match condition occurs. the pwm output function is modified by changing these two bits. it is necessary to only change the value of the t1bio1 and t1bio0 bits only after the tm has been switched off. unpredictable pwm outputs will occur if the t1bio1 and t1bio0 bits are changed when the tm is running. rev. 1.50 136 march 06 , 2012 rev. 1.50 137 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro bit 3 t1boc : tp1b_0, tp1b_1, tp1b_2 output control bit compare match output mode 0: initial low 1: initial high pwm mode/ single pulse output mode 0: active low 1: active high this is the output control bit for the tm output pin. its operation depends upon whether tm is being used in the compare match output mode or in the pwm mode/ single pulse output mode. it has no effect if the tm is in the timer/counter mode. in the compare match output mode it determines the logic level of the tm output pin before a compare match occurs. in the pwm mode it determines if the pwm signal is active high or active low. bit 2 t1bpol : tp1b_0, tp1b_1, tb1b_2 output polarity control 0: non-invert 1: invert this bit controls the polarity of the tp1b_0, tp1b_1, tp1b_2 output pin. when the bit is set high the tm output pin will be inverted and not inverted when the bit is zero. it has no effect if the tm is in the timer/counter mode. bit 1~0 t1pwm1~t1pwm0 : select pwm mode 00: edge aligned 01: centre aligned, compare match on count up 10: centre aligned, compare match on count down 11: centre aligned, compare match on count up or down tm1dl register - 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r r r r r r r r por 0 0 0 0 0 0 0 0 bit 7~0 tm1dl : tm1 counter low byte register bit 7~bit 0 tm1 10-bit counter bit 7~bit 0 tm1dh register - 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r r por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1dh : tm1 counter high byte register bit 1~bit 0 tm1 10-bit counter bit 9~bit 8 tm1al register - 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~0 tm1al : tm1 ccra low byte register bit 7~bit 0 tm1 10-bit ccra bit 7~bit 0 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 136 march 06 , 2012 rev. 1.50 137 march 06 , 2012 tm1ah register - 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1ah : tm1 ccra high byte register bit 1~bit 0 tm1 10-bit ccra bit 9~bit 8 tm1bl register - 10-bit etm bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 ~ 0 tm1bl : tm1 ccrb low byte register bit 7~bit 0 tm1 10-bit ccrb bit 7~bit 0 tm1bh register - 10-bit etm bit 7 6 5 4 3 2 1 0 name d9 d8 r/w r/w r/w por 0 0 bit 7~2 unimplemented, read as "0" bit 1~0 tm1bh : tm1 ccrb high byte register bit 1~bit 0 tm1 10-bit ccrb bit 9 ~ bit 8 enhanced type tm operating modes the enhanced type tm can operate in one of fve operating modes, compare match output mode, pwm output mode, single pulse output mode, capture input mode or timer/counter mode. the operating mode is selected using the tnam1 and tnam0 bits in the tmnc1, and the tnbm1 and tnbm0 bits in the tmnc2 register. etm operating mode ccra compare match output mode ccra timer/ counter mode ccrb pwm output mode ccrb single pulse output mode ccrb input capture mode ccrb compare match output mode ccrb timer/counter mode ccrb pwm output mode ccrb single pulse output mode ccrb input capture mode ?: permitted : not permitted rev. 1.50 138 march 06 , 2012 rev. 1.50 139 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro compare output mode to select this mode, bits tnam1, tnam0 and tnbm1, tnbm0 in the tmnc1/tmnc2 registers should be all cleared to zero. in this mode once the counter is enabled and running it can be cleared by three methods. these are a counter overfow, a compare match from comparator a and a compare match from comparator p. when the tncclr bit is low, there are two ways in which the counter can be cleared. one is when a compare match occurs from comparator p, the other is when the ccrp bits are all zero which allows the counter to overfow. here both the tnaf and tnpf interrupt request fags for comparator a and comparator p respectively, will both be generated. if the tncclr bit in the tmnc1 register is high then the counter will be cleared when a compare match occurs from comparator a. however, here only the tnaf interrupt request flag will be generated even if the value of the ccrp bits is less than that of the ccra registers. therefore when tncclr is high no tnpf interrupt request fag will be generated. as the name of the mode suggests, after a comparison is made, the tm output pin, will change state. the tm output pin condition however only changes state when an tnaf or tnbf interrupt request flag is generated after a compare match occurs from comparator a or comparator b. the tnpf interrupt request fag, generated from a compare match from comparator p, will have no effect on the tm output pin. the way in which the tm output pin changes state is determined by the condition of the tnaio1 and tnaio0 bits in the tmnc1 register for etm ccra, and the tnbio1 and tnbio0 bits in the tmnc2 register for etm ccrb. the tm output pin can be selected using the tnaio1, tnaio0 bits (for the tpna pin) and tnbio1, tnbio0 bits (for the tpnb_0, tpnb_1 or tpnb_2 pins) to go high, to go low or to toggle from its present condition when a compare match occurs from comparator a or a compare match occurs from comparator b. the initial condition of the tm output pin, which is setup after the tnon bit changes from low to high, is setup using the tnaoc or tnboc bit for tpna or tpnb_0, tpnb_1, tpnb_2 output pins. note that if the tnaio1,tnaio0 and tnbio1, tnbio0 bits are zero then no pin change will take place. counter value 0 x 3 ff ccrp ccra tnon tnpau tnapol ccrp int . flag tnpf ccra int . flag tnaf tpna o / p pin time ccrp = 0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0 ; tnam [ 1 : 0 ] = 00 output pin set to initial level low if tnaoc = 0 output toggle with tnaf flag note tnaio [ 1 : 0 ] = 10 active high output select here tnaio [ 1 : 0 ] = 11 toggle output select output not affected by tnaf flag . remains high until reset by tnon bit output pin reset to initial value output controlled by other pin - shared function output inverts when tnapol is high etm ccra compare match output mode tncclr = 0 note: 1. with tncclr=0 a comparator p match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the output pin is reset to its initial state by a tnon bit rising edge ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 138 march 06 , 2012 rev. 1.50 139 march 06 , 2012 counter value 0 x 3 ff ccrp ccrb tnon tnpau tnbpol ccrp int . flag tnpf ccrb int . flag tnbf tpnb o / p pin time ccrp = 0 ccrp > 0 counter overflow ccrp > 0 counter cleared by ccrp value pause resume stop counter restart tncclr = 0 ; tnbm [ 1 : 0 ] = 00 output pin set to initial level low if tnboc = 0 output toggle with tnbf flag note tnbio [ 1 : 0 ] = 10 active high output select here tnbio [ 1 : 0 ] = 11 toggle output select output not affected by tnbf flag . remains high until reset by tnon bit output pin reset to initial value output controlled by other pin - shared function output inverts when tnbpol is high etm ccrb compare match output mode tncclr = 0 note: 1. with tncclr=0 a comparator p match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the output pin is reset to its initial state by a tnon bit rising edge counter value 0 x 3 ff ccrp ccra tnon tnpau tnapol ccrp int . flag tnpf ccra int . flag tnaf tpna o / p pin time ccra = 0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1 ; tnam [ 1 : 0 ] = 00 output pin set to initial level low if tnaoc = 0 output toggle with tnaf flag note tnaio [ 1 : 0 ] = 10 active high output select here tnaio [ 1 : 0 ] = 11 toggle output select output not affected by tnaf flag . remains high until reset by tnon bit output pin reset to initial value output controlled by other pin - shared function output inverts when tnapol is high tnpf not generated no tnaf flag generated on ccra overflow output does not change etm ccra compare match output mode tncclr = 1 note: 1. with tncclr=1 a comparator a match will clear the counter 2. the tpna output pin is controlled only by the tnaf fag 3. the tpna output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 rev. 1.50 140 march 06 , 2012 rev. 1.50 141 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro counter value 0 x 3 ff ccrb ccra tnon tnpau tnbpol ccrb int . flag tnbf ccra int . flag tnaf tpnb o / p pin time ccra = 0 ccra = 0 counter overflow ccra > 0 counter cleared by ccra value pause resume stop counter restart tncclr = 1 ; tnbm [ 1 : 0 ] = 00 output pin set to initial level low if tnboc = 0 output toggle with tnbf flag note tnbio [ 1 : 0 ] = 10 active high output select here tnbio [ 1 : 0 ] = 11 toggle output select output not affected by tnbf flag . remains high until reset by tnon bit output pin reset to initial value output controlled by other pin - shared function output inverts when tnbpol is high no tnaf flag generated on ccra overflow etm ccrb compare match output mode tncclr = 1 note: 1. with tncclr=1 a comparator a match will clear the counter 2. the tpnb output pin is controlled only by the tnbf fag 3. the tpnb output pin is reset to its initial state by a tnon bit rising edge 4. the tnpf fag is not generated when tncclr=1 timer/counter mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 11 respectively. the timer/counter mode operates in an identical way to the compare match output mode generating the same interrupt fags. the exception is that in the timer/counter mode the tm output pin is not used. therefore the above description and timing diagrams for the compare match output mode can be used to understand its function. as the tm output pin is not used in this mode, the pin can be used as a normal i/o pin or other pin-shared function. pwm output mode to select this mode, bits tnm1 and tnm0 in the tmnc1 register should be set to 10 respectively and also the tnio1 and tnio0 bits should be set to 10 respectively. the pwm function within the tm is useful for applications which require functions such as motor control, heating control, illumination control etc. by providing a signal of fxed frequency but of varying duty cycle on the tm output pin, a square wave ac waveform can be generated with varying equivalent dc rms values. as both the period and duty cycle of the pwm waveform can be controlled, the choice of generated waveform is extremely flexible. in the pwm mode, the tncclr bit has no effect as the pwm period. both of the ccra and ccrp registers are used to generate the pwm waveform, one register is used to clear the internal counter and thus control the pwm waveform frequency, while the other one is used to control the duty cycle. which register is used to control either frequency or duty cycle is determined using the tndpx bit in the tmnc1 register. the pwm waveform frequency and duty cycle can therefore be controlled by the values in the ccra and ccrp registers. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 140 march 06 , 2012 rev. 1.50 141 march 06 , 2012 an interrupt fag, one for each of the ccra and ccrp, will be generated when a compare match occurs from either comparator a or comparator p. the tnoc bit in the tmnc1 register is used to select the required polarity of the pwm waveform while the two tnio1 and tnio0 bits are used to enable the pwm output or to force the tm output pin to a fxed high or low level. the tnpol bit is used to reverse the polarity of the pwm output waveform. etm, pwm mode, edge aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 128 256 384 512 640 768 896 1024 a duty ccra b duty ccrb if f sys = 16mhz, tm clock source select f sys /4, ccrp = 100b, ccra = 128 and ccrb = 256, the tp1a pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125khz, duty = 128/512 = 25%. the tp1b_n pwm output frequency = (f sys /4) / 512 = f sys /2048 = 7.8125khz, duty = 256/512 = 50%. if the duty value defned by ccra or ccrb register is equal to or greater than the period value, then the pwm output duty is 100%. etm, pwm mode, edge aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 period 1 2 3 511 512 1021 1022 1023 b duty ccrb etm, pwm mode, center aligned mode, tncclr=0 ccrp 001b 010b 011b 100b 101b 110b 111b 000b period 256 512 768 1024 1280 1536 1792 2046 a duty (ccrax2)-1 b duty (ccrbx2)-1 etm, pwm mode, center aligned mode, tncclr=1 ccra 1 2 3 511 512 1021 1022 1023 period 2 4 6 1022 1024 2042 2044 2046 b duty (ccrbx2)-1 rev. 1.50 142 march 06 , 2012 rev. 1.50 143 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro counter value ccrp ccra tnon tnpau tnapol ccra int . flag tnaf ccrb int . flag tnbf tpna pin ( tnaoc = 1 ) time counter cleared by ccrp pause resume stop counter restart tncclr = 0 ; tnam [ 1 : 0 ] = 10, tnbm [ 1 : 0 ] = 10; tnpwm [ 1 : 0 ] = 00 output pin reset to initial value output controlled by other pin - shared function output inverts when tnapol is high ccrb ccrp int . flag tnpf tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) duty cycle set by ccra duty cycle set by ccrb pwm period set by ccrp duty cycle set by ccra duty cycle set by ccra etm pwm mode edge aligned note: 1. here tncclr=0 therefore ccrp clears counter and determines the pwm period 2. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 3. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty counter value ccra tnon tnpau tnbpol ccrb int . flag tnbf time counter cleared by ccra pause resume stop counter restart tncclr = 1 ; tnbm [ 1 : 0 ] = 10; tnpwm [ 1 : 0 ] = 00 output pin reset to initial value output controlled by other pin - shared function output inverts when tnbpol is high ccrb ccrp int . flag tnpf tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) duty cycle set by ccrb pwm period set by ccra etm pwm mode edge aligned note: 1. here tncclr=1, therefore ccra clears the counter and determines the pwm period 2. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 3. the ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 4. here the tm pin control register should not enable the tpna pin as a tm output pin. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 142 march 06 , 2012 rev. 1.50 143 march 06 , 2012 counter value ccrp ccra tnon tnpau tnapol ccra int . flag tnaf ccrb int . flag tnbf tpna pin ( tnaoc = 1 ) time pause resume stop counter restart tncclr = 0 ; tnam [ 1 : 0 ] = 10, tnbm [ 1 : 0 ] = 10; tnpwm [ 1 : 0 ] = 11 output pin reset to initial value output controlled by other pin - shared function output inverts when tnapol is high ccrb ccrp int . flag tnpf tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) duty cycle set by ccra duty cycle set by ccrb pwm period set by ccrp etm pwm mode centre aligned note: 1. here tncclr=0 therefore ccrp clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnaio [1:0] (or tnbio [1:0]) = 00 or 01 4. ccra controls the tpna pwm duty and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value counter value ccra tnon tnpau tnbpol ccra int . flag tnaf ccrb int . flag tnbf time pause resume stop counter restart tncclr = 1 ; tnbm [ 1 : 0 ] = 10; tnpwm [ 1 : 0 ] = 11 output pin reset to initial value output controlled by other pin - shared function ccrb tpnb pin ( tnboc = 1 ) tpnb pin ( tnboc = 0 ) duty cycle set by ccrb pwm period set by ccra output inverts when tnbpol is high ccrp int . flag tnpf etm pwm mode centre aligned note: 1. here tncclr=1 therefore ccra clears the counter and determines the pwm period 2. tnpwm [1:0] =11 therefore the pwm is centre aligned 3. the internal pwm function continues running even when tnbio [1:0] = 00 or 01 4. ccra controls the tpnb pwm period and ccrb controls the tpnb pwm duty 5. ccrp will generate an interrupt request when the counter decrements to its zero value rev. 1.50 144 march 06 , 2012 rev. 1.50 145 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro single pulse mode to select this mode, the required bit pairs, tnam1, tnam0 and tnbm1, tnbm0 should be set to 10 respectively and also the corresponding tnaio1, tnaio0 and tnbio1, tnbio0 bits should be set to 11 respectively. the single pulse output mode, as the name suggests, will generate a single shot pulse on the tm output pin. the trigger for the pulse tpna output leading edge is a low to high transition of the tnon bit, which can be implemented using the application program. the trigger for the pulse tpnb output leading edge is a compare match from comparator b, which can be implemented using the application program. however in the single pulse mode, the tnon bit can also be made to automatically change from low to high using the external tckn pin, which will in turn initiate the single pulse output of tpna. when the tnon bit transitions to a high level, the counter will start running and the pulse leading edge of tpna will be generated. the tnon bit should remain high when the pulse is in its active state. the generated pulse trailing edge of tpna and tpnb will be generated when the tnon bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from comparator a. however a compare match from comparator a will also automatically clear the tnon bit and thus generate the single pulse output trailing edge of tpna and tpnb. in this way the ccra value can be used to control the pulse width of tpna. the ccra-ccrb value can be used to control the pulse width of tpnb. a compare match from comparator a and comparator b will also generate tm interrupts. the counter can only be reset back to zero when the tnon bit changes from low to high when the counter restarts. in the single pulse mode ccrp is not used. the tncclr bit is also not used. tnon bit 0 ? 1 s/ w command set ? tnon ? or tckn pin transition ccrb leading edge tnon bit 1 ? 0 ccra trailing edge s/ w command clr ? tnon ? or ccra compare match tpna output pin tpnb output pin pulse width = ( ccra -ccrb ) value pulse width = ccra value counter value ccrb ccra 0 time tnon = 1 ccrb compare match tnon bit 1 ? 0 s/ w command clr ? tnon ? or ccra compare match ccrb trailing edge ccra leading edge single pulse generation ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 144 march 06 , 2012 rev. 1.50 145 march 06 , 2012 single pulse mode note: 1. counter stopped by ccra 2. ccrp is not used 3. the pulse is triggered by the tckn pin or by setting the tnon bit high 4. a tckn pin active edge will automatically set the tnon bit high 5. in the single pulse mode, tnaio [1:0] and tnbio [1:0] must be set to 11 and can not be changed. rev. 1.50 146 march 06 , 2012 rev. 1.50 147 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro capture input mode to select this mode bits tnam 1, tnam0 and tnbm1, tnbm0 in the tmnc1 and tmnc2 registers should be set to 01 respectively. this mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. the external signal is supplied on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the tnaio1, tnaio0 and tnbio1, tnbio0 bits in the tmnc1 and tmnc2 registers. the counter is started when the tnon bit changes from low to high which is initiated using the application program. when the required edge transition appears on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the present value in the counter will be latched into the ccra and ccrb registers and a tm interrupt generated. irrespective of what events occur on the tpna and tpnb_0, tpnb_1, tpnb_2 pins the counter will continue to free run until the tnon bit changes from high to low. when a ccrp compare match occurs the counter will reset back to zero; in this way the ccrp value can be used to control the maximum counter value. when a ccrp compare match occurs from comparator p, a tm interrupt will also be generated. counting the number of overfow interrupt signals from the ccrp can be a useful method in measuring long pulse widths. the tnaio1, tnaio0 and tnbio1, tnbio0 bits can select the active trigger edge on the tpna and tpnb_0, tpnb_1, tpnb_2 pins to be a rising edge, falling edge or both edge types. if the tnaio1, tnaio0 and tnbio1, tnbio0 bits are both set high, then no capture operation will take place irrespective of what happens on the tpna and tpnb_0, tpnb_1, tpnb_2 pins, however it must be noted that the counter will continue to run. as the tpna and tpnb_0, tpnb_1, tpnb_2 pins are pin shared with other functions, care must be taken if the tm is in the capture input mode. this is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. the tncclr, tnaoc, tnboc, tnapol and tnbpol bits are n ot used in this mode. etm ccra capture input mode note: 1. tnam [1:0] = 01 and active edge set by the tnaio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccra 3. tncclr bit not used 4. no output function C tnaoc and tnapol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 146 march 06 , 2012 rev. 1.50 147 march 06 , 2012 etm ccrb capture input mode note: 1. tnbm [1:0] = 01 and active edge set by the tnbio [1:0] bits 2. the tm capture input pin active edge transfers the counter value to ccrb 3. tncclr bit not used 4. no output function C tnboc and tnbpol bits not used 5. ccrp determines the counter value and the counter has a maximum count value when ccrp is equal to zero. rev. 1.50 148 march 06 , 2012 rev. 1.50 149 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro analog to digital converter the need to interface to real world analog signals is a common requirement for many electronic systems. however, to properly process these signals by a microcontroller, they must first be converted into digital signals by a/d converters. by integrating the a/d conversion electronic circuitry into the microcontroller, the need for external components is reduced signifcantly with the corresponding follow-on benefts of lower costs and reduced component space requirements. a/d overview the devices contains a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into either a 12-bit digital value. part no. input channels a/d channel select bits input pins ht67f30 ht67f40 HT67F50 8 acs4, acs2~acs0 an0~an7 ht67f60 12 acs4, acs3~acs0 an0~an11 the accompanying block diagram shows the overall internal structure of the a/d converter, together with its associated registers. a/d converter register description overall operation of the a/d converter is controlled using six registers. a read only register pair exists to store the adc data 12-bit value. the remaining three or four registers are control registers which setup the operating and control function of the a/d converter. register name bit 7 6 5 4 3 2 1 0 adrl(adrfs=0) d3 d2 d1 d0 adrl(adrfs=1) d7 d6 d5 d4 d3 d2 d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d7 d6 d5 d4 adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs2 acs1 acs0 adcr1 acs4 v125en vrefs adck2 adck1 adck0 acerl ace7 ace6 ace5 ace4 ace3 ace2 ace1 ace0 ht67f30/ht67f40/HT67F50 a/d converter register list register name bit 7 6 5 4 3 2 1 0 adrl(adrfs=0) d3 d2 d1 d0 adrl(adrfs=1) d7 d6 d5 d4 d3 d2 d1 d0 adrh(adrfs=0) d11 d10 d9 d8 d7 d6 d5 d4 adrh(adrfs=1) d11 d10 d9 d8 adcr0 start eocb adoff adrfs acs3 acs2 acs1 acs0 adcr1 acs4 v125en vrefs adck2 adck1 adck0 acerl ace7 ace6 ace5 ace4 ace3 ace2 ace1 ace0 acerh ace11 ace10 ace9 ace8 ht67f60 a/d converter register list ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 148 march 06 , 2012 rev. 1.50 149 march 06 , 2012 ?? ?? ? ?? ? ?- - ?? ? ? ?- ? ? ?? ? ? ? ?? ? ? ? ? ?- - ? ?- ? ? - ? ? ? ? ? ? a/d converter structure a/d converter data registers C adrl, adrh as the devices contain an internal 12-bit a/d converter, they require two data registers to store the converted value. these are a high byte register, known as adrh, and a low byte register, known as adrl. after the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. as only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the adrfs bit in the adcr0 register as shown in the accompanying table. d0~d11 are the a/d conversion result data bits. any unused bits will be read as zero. adrfs adrh adrl 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 1 0 0 0 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a/d data registers a/d converter control registers C adcr0, adcr1, acerl, acerh to control the function and operation of the a/d converter, three or four control registers known as adcr0, adcr1, acerl and acerh are provided. these 8-bit registers defne functions such as the selection of which analog channel is connected to the internal a/d converter, the digitised data format, the a/d clock source as well as controlling the start function and monitoring the a/d converter end of conversion status. the acs3~acs0 bits in the adcr0 register and acs4 bit is the adcr1 register define the adc input channel number. as the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 or 12 analog inputs must be routed to the converter. it is the function of the acs4~acs0 bits to determine which analog channel input pins or internal 1.25v is actually connected to the internal a/d converter. the acerh and acerl control registers contain the acer11~acer0 bits which determine which pins on port a, ph0~ph3 are used as analog inputs for the a/d converter input and which pins are not to be used as the a/d converter input. setting the corresponding bit high will select the a/d input function, clearing the bit to zero will select either the i/o or other pin-shared function. when the pin is selected to be an a/d input, its original function whether it is an i/o or other pin- shared function will be removed. in addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an a/d input. rev. 1.50 150 march 06 , 2012 rev. 1.50 151 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro adcr0 register ht67f30/ht67f40/HT67F50 bit 7 6 5 4 3 2 1 0 name start eocb adoff adrfs acs2 acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 bit 7 start : start the a/d conversion 010: start 01 : reset the a/d converter and set eocb to "1" this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the device power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs : adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3 unimplemented, read as "0" bit 2~0 acs2, acs1, acs0 : select a/d channel (when acs4 is "0") 000: an0 001: an1 010: an2 011: an3 100: an4 101: an5 110: an6 111: an7 these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.25v will be routed to the a/d converter. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 150 march 06 , 2012 rev. 1.50 151 march 06 , 2012 ht67f60 bit 7 6 5 4 3 2 1 0 name start eocb adoff adrfs acs3 acs2 acs1 acs0 r/w r/w r r/w r/w r/w r/w r/w r/w por 0 1 1 0 0 0 0 0 bit 7 start : start the a/d conversion 010: start 01: reset the a/d converter and set eocb to "1" this bit is used to initiate an a/d conversion process. the bit is normally low but if set high and then cleared low again, the a/d converter will initiate a conversion process. when the bit is set high the a/d converter will be reset. bit 6 eocb : end of a/d conversion fag 0: a/d conversion ended 1: a/d conversion in progress this read only fag is used to indicate when an a/d conversion process has completed. when the conversion process is running the bit will be high. bit 5 adoff : adc module power on/off control bit 0: adc module power on 1: adc module power off this bit controls the power to the a/d internal function. this bit should be cleared to zero to enable the a/d converter. if the bit is set high then the a/d converter will be switched off reducing the device power consumption. as the a/d converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. note: 1. it is recommended to set adoff=1 before entering idle/sleep mode for saving power. 2. adoff=1 will power down the adc module. bit 4 adrfs : adc data format control 0: adc data msb is adrh bit 7, lsb is adrl bit 4 1: adc data msb is adrh bit 3, lsb is adrl bit 0 this bit controls the format of the 12-bit converted a/d value in the two a/d data registers. details are provided in the a/d data register section. bit 3~0 acs3, acs2, acs1, acs0 : select a/d channel (when acs4 is "0") 0000: an0 0001: an1 0010: an2 0011: an3 0100: an4 0101: an5 0110: an6 0111: an7 1000: an8 1001: an9 1010: an10 1011: an11 1100~1111: undefned, can't be used these are the a/d channel select control bits. as there is only one internal hardware a/d converter each of the eight a/d inputs must be routed to the internal converter using these bits. if bit acs4 in the adcr1 register is set high then the internal 1.25v will be routed to the a/dconverter. rev. 1.50 152 march 06 , 2012 rev. 1.50 153 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro adcr1 register bit 7 6 5 4 3 2 1 0 name acs4 v125en vrefs adck2 adck1 adck0 r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 acs4 : selecte internal 1.25v as adc input control 0: disable 1: enable this bit enables 1.25v to be connected to the a/d converter. the v125en bit must frst have been set to enable the bandgap circuit 1.25v voltage to be used by the a/d converter. when the acs4 bit is set high, the bandgap 1.25v voltage will be routed to the a/d converter and the other a/d input channels disconnected. bit 6 v125en : internal 1.25v control 0: disable 1: enable this bit controls the internal bandgap circuit on/off function to the a/d converter. when the bit is set high the bandgap voltage 1.25v can be used by the a/d converter. if 1.25v is not used by the a/d converter and the lvr/lvd function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. when 1.25v is switched on for use by the a/d converter, a time t bg should be allowed for the bandgap circuit to stabilise before implementing an a/d conversion. bit 5 unimplemented, read as "0" bit 4 vrefs : selecte adc reference voltage 0: internal adc power 1: vref pin this bit is used to select the reference voltage for the a/d converter. if the bit is high, then the a/d converter reference voltage is supplied on the external vref pin. if the pin is low, then the internal reference is used which is taken from the power supply pin vdd. bit 3 unimplemented, read as "0" bit 2~0 adck2, adck1, adck0 : select adc clock source 000: f sys 001: f sys /2 010: f sys /4 011: f sys /8 100: f sys /16 101: f sys /32 110: f sys /64 111: undefned these three bits are used to select the clock source for the a/d converter. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 152 march 06 , 2012 rev. 1.50 153 march 06 , 2012 acerl register bit 7 6 5 4 3 2 1 0 name ace7 ace6 ace5 ace4 ace3 ace2 ace1 ace0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ace7 : defne pa7 is a/d input or not 0: not a/d input 1: a/d input, an7 bit 6 ace6 : defne pa6 is a/d input or not 0: not a/d input 1: a/d input, an6 bit 5 ace5 : defne pa5 is a/d input or not 0: not a/d input 1: a/d input, an5 bit 4 ace4 : defne pa4 is a/d input or not 0: not a/d input 1: a/d input, an4 bit 3 ace3 : defne pa3 is a/d input or not 0: not a/d input 1: a/d input, an3 bit 2 ace2 : defne pa2 is a/d input or not 0: not a/d input 1: a/d input, an2 bit 1 ace1 : defne pa1 is a/d input or not 0: not a/d input 1: a/d input, an1 bit 0 ace0 : defne pa0 is a/d input or not 0: not a/d input 1: a/d input, an0 acerh register ht67f60 bit 7 6 5 4 3 2 1 0 name ace11 ace10 ace9 ace8 r/w r/w r/w r/w r/w por 1 1 1 1 bit 7~4 unimplemented, read as "0" bit 3 ace11 : defne ph3 is a/d input or not 0: not a/d input 1: a/d input, an11 bit 2 ace10 : defne ph2 is a/d input or not 0: not a/d input 1: a/d input, an10 bit 1 ace9 : defne ph1 is a/d input or not 0: not a/d input 1: a/d input, an9 bit 0 ace8 : defne ph0 is a/d input or not 0: not a/d input 1: a/d input, an8 rev. 1.50 154 march 06 , 2012 rev. 1.50 155 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro a/d operation the start bit in the adcr0 register is used to start and reset the a/d converter. when the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. when the start bit is brought from low to high but not low again, the eocb bit in the adcr0 register will be set high and the analog to digital converter will be reset. it is the start bit that is used to control the overall start operation of the internal analog to digital converter. the eocb bit in the adcr0 register is used to indicate when the analog to digital conversion process is complete. this bit will be automatically set to "0" by the microcontroller after a conversion cycle has ended. in addition, the corresponding a/d interrupt request fag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. this a/d internal interrupt signal will direct the program fow to the associated a/ d internal interrupt address for processing. if the a/d internal interrupt is disabled, the microcontroller can be used to poll the eocb bit in the adcr0 register to check whether it has been cleared as an alternative method of detecting the end of an a/d conversion cycle. the clock source for the a/d converter, which originates from the system clock f sys , can be chosen to be either f sys or a subdivided version of f sys the division ratio value is determined by the adck2~adck0 bits in the adcr1 register. although the a/d clock source is determined by the system clock f sys , and by bits adck2~adck0, there are some limitations on the maximum a/d clock source speed that can be selected. as the minimum value of permissible a/d clock period, t adck , is 0.5ms, care must be taken for system clock frequencies equal to or greater than 4mhz. for example, if the system clock operates at a frequency of 4mhz, the adck2~adck0 bits should not be set to "000". doing so will give a/d clock periods that are less than the minimum a/d clock period which may result in inaccurate a/d conversion values. refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specifed minimum a/d clock period. f sys a/d clock period (t adck ) adck2, adck1, adck0 =000 (f sys ) adck2, adck1, adck0 =001 (f sys /2) adck2, adck1, adck0 =010 (f sys /4) adck2, adck1, adck0 =011 (f sys /8) adck2, adck1, adck0 =100 (f sys /16) adck2, adck1, adck0 =101 (f sys /32) adck2, adck1, adck0 =110 (f sys /64) adck2, adck1, adck0 =111 1mhz 1s 2s 4s 8s 16s 32s 64s undefned 2mhz 500ns 1s 2s 4s 8s 16s 32s undefned 4mhz 250ns* 500ns 1s 2s 4s 8s 16s undefned 8mhz 125ns* 250ns* 500ns 1s 2s 4s 8s undefned 12mhz 83ns* 167ns* 333ns* 667ns 1.33s 2.67s 5.33s undefned a/d clock period examples controlling the power on/off function of the a/d converter circuitry is implemented using the adoff bit in the adcr0 register. this bit must be zero to power on the a/d converter. when the adoff bit is cleared to zero to power on the a/d converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an a/d conversion is initiated. even if no pins are selected for use as a/d inputs by clearing the ace11~ace0 bits in the acerh and acerl registers, if the adoff bit is zero then some power will still be consumed. in power conscious applications it is therefore recommended that the adoff is set high to reduce power consumption when the a/d converter function is not being used. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 154 march 06 , 2012 rev. 1.50 155 march 06 , 2012 the reference voltage supply to the a/d converter can be supplied from either the positive power supply pin, v dd , or from an external reference sources supplied on pin vref. the desired selection is made using the vrefs bit. as the vref pin is pin-shared with other functions, when the vrefs bit is set high, the vref pin function will be selected and the other pin functions will be disabled automatically. a/d input pins all of the a/d analog input pins are pin-shared with the i/o pins on port a, ph0~ph3 as well as other functions. the ace11~ ace0 bits in the acerh and acerl registers, determine whether the input pins are setup as a/d converter analog inputs or whether they have other functions. if the ace11~ ace0 bits for its corresponding pin is set high then the pin will be setup to be an a/d converter input and the original pin functions disabled. in this way, pins can be changed under program control to change their function between a/d inputs and other functions. all pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as a/d inputs. note that it is not necessary to frst setup the a/d pin as an input in the pac or phc port control register to enable the a/d input as when the ace11~ ace0 bits enable an a/d input, the status of the port control register will be overridden. the a/d converter has its own reference voltage pin, vref, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the vrefs bit in the adcr1 register. the analog input values must not be allowed to exceed the value of vref. ? ? ? ? ? ? ?? ? - a/d input structure rev. 1.50 156 march 06 , 2012 rev. 1.50 157 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro summary of a/d conversion steps the following summarises the individual steps that should be executed in order to implement an a/ d conversion process. step 1 select the required a/d conversion clock by correctly programming bits adck2~adck0 in the adcr1 register. step 2 enable the a/d by clearing the adoff bit in the adcr0 register to zero. step 3 select which channel is to be connected to the internal a/d converter by correctly programming the acs4~acs0 bits which are also contained in the adcr1 and adcr0 register. step 4 select which pins are to be used as a/d inputs and confgure them by correctly programming the ace11~ace0 bits in the acerh and acerl registers. step 5 if the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the a/d converter interrupt function is active. the master interrupt control bit, emi, and the a/d converter interrupt bit, eadi, must both be set high to do this. step 6 the analog to digital conversion process can now be initialised by setting the start bit in the adcr register from low to high and then low again. note that this bit should have been originally cleared to zero. step 7 to check when the analog to digital conversion process is complete, the eocb bit in the adcr0 register can be polled. the conversion process is complete when this bit goes low. when this occurs the a/d data registers adrl and adrh can be read to obtain the conversion value. as an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an a/d interrupt to occur. note: when checking for the end of the conversion process, if the method of polling the eocb bit in the adcr0 register is used, the interrupt enable step above can be omitted. ?? ? ? ? ??? ? ? ? ? ? ? ? ? ? ? ? ? ? - ? ? ? ? ?? - a/d conversion timing ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 156 march 06 , 2012 rev. 1.50 157 march 06 , 2012 the accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. after an a/d conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. the time taken for the a/d conversion is 16t adck where t adck is equal to the a/d clock period. programming considerations during microcontroller operations where the a/d converter is not being used, the a/d internal circuitry can be switched off to reduce power consumption, by setting bit adoff high in the adcr0 register. when this happens, the internal a/d converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. if the a/d converter input lines are used as normal i/os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. a/d transfer function as the devices contain a 12-bit a/d converter, its full-scale converted digitised value is equal to fffh. since the full-scale analog input value is equal to the v dd or v ref voltage, this gives a single bit analog input value of v dd or vref divided by 4096. 1 lsb= (v dd or v ref ) 4096 the a/d converter input voltage value can be calculated using the following equation: a/d input voltage = a/d output digital value (v dd or v ref ) 4096 the diagram shows the ideal transfer function between the analog input value and the digitised output value for the a/d converter. except for the digitised zero value, the subsequent digitised values will change at a point 0.5 lsb below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 lsb below the v dd or v ref level. a/d programming example the following two programming examples illustrate how to setup and implement an a/d conversion. in the frst example, the method of polling the eocb bit in the adcr0 register is used to detect when the conversion cycle is complete, whereas in the second example, the a/d interrupt is used to determine when the conversion is complete. ? ? ? ? ? ? ?? ? ? ? ideal a/d transfer function rev. 1.50 158 march 06 , 2012 rev. 1.50 159 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro example: using an eocb polling method to detect the end of conversion clr eadi ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,0fh ; setup acerl and acerh to confgure pins an0~an3 mov acerl,a mov a,00h mov acerh,00h ; acerh is only for ht67f60 mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter : start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d polling_eoc: sz eocb ; poll the adcr0 register eocb bit to detect end ; of a/d conversion jmp polling_eoc ; continue polling mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : jmp start_convers ion ; start next a/d conversion example: using the interrupt method to detect the end of conversion clr eadi ; disable adc interrupt mov a,03h mov adcr1,a ; select f sys /8 as a/d clock and switch off 1.25v clr adoff mov a,0fh ; setup acerl and acerh to confgure pins an0~an3 mov acerl,a mov a,00h mov acerh,00h ; acerh is only for ht67f60 mov a,00h mov adcr0,a ; enable and connect an0 channel to a/d converter start_conversion: clr start ; high pulse on start bit to initiate conversion set start ; reset a/d clr start ; start a/d clr adf ; clear adc interrupt request fag set eadi ; enable adc interrupt set emi ; enable global interrupt : : ; adc interrupt service routine adc_isr: mov acc_stack,a ; save acc to user defned memory mov a,status mov status_stack,a ; save status to user defned memory : : mov a,adrl ; read low byte conversion result value mov adrl_buffer,a ; save result to user defned register mov a,adrh ; read high byte conversion result value mov adrh_buffer,a ; save result to user defned register : : exit_int_isr: mov a,status_stack mov status,a ; restore status from user defned memory mov a,acc_stack ; restore acc from user defned memory reti ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 158 march 06 , 2012 rev. 1.50 159 march 06 , 2012 comparators two independent analog comparators are contained within these devices. these functions offer fexibility via their register controlled features such as power-down, polarity select, hysteresis etc. in sharing their pins with normal i/o pins the comparators do not waste precious i/o pins if there functions are otherwise unused. comparator comparator operation the device contains two comparator functions which are used to compare two analog voltages and provide an output based on their difference. full control over the two internal comparators is provided via two control registers, cp0c and cp1c, one assigned to each comparator. the comparator output is recorded via a bit in their respective control register, but can also be transferred out onto a shared i/o pin. additional comparator functions include, output polarity, hysteresis functions and power down control. any pull-high resistors connected to the shared comparator input pins will be automatically disconnected when the comparator is enabled. as the comparator inputs approach their switching level, some spurious output signals may be generated on the comparator output due to the slow rising or falling nature of the input signals. this can be minimised by selecting the hysteresis function will apply a small amount of positive feedback to the comparator. ideally the comparator should switch at the point where the positive and negative inputs signals are at the same voltage level, however, unavoidable input offsets introduce some uncertainties here. the hysteresis function, if enabled, also increases the switching offset value. comparator registers there are two registers for overall comparator operation, one for each comparator. as corresponding bits in the two registers have identical functions, they following register table applies to both registers. register name bit 7 6 5 4 3 2 1 0 cp0c c0sel c0en c0pol c0out c0os c0hyen cp1c c1sel c1en c1pol c1out c1os c1hyen comparator registers list comparator interrupt each also possesses its own interrupt function. when any one of the changes state, its relevant interrupt flag will be set, and if the corresponding interrupt enable bit is set, then a jump to its relevant interrupt vector will be executed. note that it is the changing state of the c0out or c1out bit and not the output pin which generates an interrupt. if the microcontroller is in the sleep or idle mode and the comparator is enabled, then if the external input lines cause the comparator output to change state, the resulting generated interrupt fag will also generate a wake-up. if it is required to disable a wake-up from occurring, then the interrupt fag should be frst set high before entering the sleep or idle mode. rev. 1.50 160 march 06 , 2012 rev. 1.50 161 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro programming considerations if the comparator is enabled, it will remain active when the microcontroller enters the sleep or idle mode, however as it will consume a certain amount of power, the user may wish to consider disabling it before the sleep or idle mode is entered. as comparator pins are shared with normal i/o pins the i/o registers for these pins will be read as zero (port control register is "1") or read as port data register value (port control register is "0") if the comparator function is enabled. cp0c register bit 7 6 5 4 3 2 1 0 name c0sel c0en c0pol c0out c0os c0hyen r/w r/w r/w r/w r r/w r/w por 1 0 0 0 0 1 bit 7 c0sel : select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 c0en : comparator on/off control 0: off 1: on this is the comparator on/off control bit. if the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the sleep or idle mode. bit 5 c0pol : comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c0out bit will refect the non-inverted output condition of the comparator. if the bit is high the comparator c0out bit will be inverted. bit 4 c0out : comparator output bit c0pol=0 0: c0+ < c0- 1: c0+ > c0- c0pol=1 0: c0+ > c0- 1: c0+ < c0- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c0pol bit. bit 3 c0os : output path select 0: c0x pin 1: internal use this is the comparator output path select control bit. if the bit is set to "0" and the c0sel bit is "1" the comparator output is connected to an external c0x pin. if the bit is set to "1" or the c0sel bit is "0" the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as "0" bit 0 c0hyen : hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 160 march 06 , 2012 rev. 1.50 161 march 06 , 2012 cp1c register bit 7 6 5 4 3 2 1 0 name c1sel c1en c1pol c1out c1os c1hyen r/w r/w r/w r/w r r/w r/w por 1 0 0 0 0 1 bit 7 c1sel : select comparator pins or i/o pins 0: i/o pin select 1: comparator pin select this is the comparator pin or i/o pin select bit. if the bit is high the comparator will be selected and the two comparator input pins will be enabled. as a result, these two pins will lose their i/o pin functions. any pull-high confguration options associated with the comparator shared pins will also be automatically disconnected. bit 6 c1en : comparator on/off control 0: off 1: on this is the comparator on/off control bit. if the bit is zero the comparator will be switched off and no power consumed even if analog voltages are applied to its inputs. for power sensitive applications this bit should be cleared to zero if the comparator is not used or before the device enters the sleep or idle mode. bit 5 c1pol : comparator output polarity 0: output not inverted 1: output inverted this is the comparator polarity bit. if the bit is zero then the c1out bit will refect the non-inverted output condition of the comparator. if the bit is high the comparator c1out bit will be inverted. bit 4 c1out : comparator output bit c1pol=0 0: c1+ < c1- 1: c1+ > c1- c1pol=1 0: c1+ > c1- 1: c1+ < c1- this bit stores the comparator output bit. the polarity of the bit is determined by the voltages on the comparator inputs and by the condition of the c1pol bit. bit 3 c1os : output path select 0: c1x pin 1: internal use this is the comparator output path select control bit. if the bit is set to "0" and the c1sel bit is "1" the comparator output is connected to an external c1x pin. if the bit is set to "1" or the c1sel bit is "0" the comparator output signal is only used internally by the device allowing the shared comparator output pin to retain its normal i/o operation. bit 2~1 unimplemented, read as "0" bit 0 c1hyen : hysteresis control 0: off 1: on this is the hysteresis control bit and if set high will apply a limited amount of hysteresis to the comparator, as specifed in the comparator electrical characteristics table. the positive feedback induced by hysteresis reduces the effect of spurious switching near the comparator threshold. rev. 1.50 162 march 06 , 2012 rev. 1.50 163 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro serial interface module C sim these devices contain a serial interface module, which includes both the four line spi interface or the two line i 2 c interface types, to allow an easy method of communication with external peripheral hardware. having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external spi or i 2 c based hardware such as sensors, flash or eeprom memory, etc. the sim interface pins are pin-shared with other i/o pins therefore the sim interface function must frst be selected using a confguration option. as both interface types share the same pins and registers, the choice of whether the spi or i 2 c type is used is made using the sim operating mode control bits, named sim2~sim0, in the simc0 register. these pull-high resistors of the sim pin-shared i/o are selected using pull-high control registers, and also if the sim function is enabled. spi interface this spi interface function which is contained within the serial interface module, should not be confused with the other independent spi function, known as spia, which is described in another section of this datasheet. the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spi interface specifcation can control multiple slave devices from a single master, but this device provided only one scs pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pin to select the slave devices. spi interface operation the spi interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdi, sdo, sck and scs . pins sdi and sdo are the serial data input and serial data output lines, sck is the serial clock line and scs is the slave select line. as the spi interface pins are pin-shared with normal i/o pins and with the i 2 c function pins, the spi interface must frst be enabled by selecting the sim enable confguration option and setting the correct bits in the simc0 and simc2 registers. after the spi confguration option has been confgured it can also be additionally disabled or enabled using the simen bit in the simc0 register. communication between devices connected to the spi interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as the device only contains a single scs pin only one slave device can be utilized. the scs pin is controlled by software, set csen bit to "1" to enable scs pin function, set csen bit to "0" the scs pin will be foating state. spi master/slave connection ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 162 march 06 , 2012 rev. 1.50 163 march 06 , 2012 ? ? ? ? ? ? ? ? ? ? - ? ? ? ? ? ? ? ? ? ? spi block diagram the spi function in this device offers the following features: full duplex synchronous data transfer both master and slave modes lsb frst or msb frst data transmission modes transmission complete fag rising or falling active clock edge wcol and csen bit enabled or disable select the status of the spi interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as csen and simen. there are several confguration options associated with the spi interface. one of these is to enable the sim function which selects the sim pins rather than normal i/o pins. note that if the confguration option does not select the sim function then the simen bit in the simc0 register will have no effect. another two spi confguration options determine if the csen and wcol bits are to be used. rev. 1.50 164 march 06 , 2012 rev. 1.50 165 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro spi registers there are three internal registers which control the overall operation of the spi interface. these are the simd data register and two registers simc0 and simc2. note that the simc1 register is only used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim2 sim1 sim0 pcken pckp1 pckp0 simen simd d7 d6 d5 d4 d3 d2 d1 d0 simc2 d7 d6 ckpolb ckeg mls csen wcol trf sim registers list the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknow there are also two control registers for the spi interface, simc0 and simc2. note that the simc2 register also has the name sima which is used by the i 2 c function. the simc1 register is not used by the spi function, only by the i 2 c function. register simc0 is used to control the enable/disable function and to set the data transmission clock frequency. although not connected with the spi function, the simc0 register is also used to control the peripheral clock prescaler. register simc2 is used for other control functions such as lsb/msb selection, write collision fag etc. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 164 march 06 , 2012 rev. 1.50 165 march 06 , 2012 simc0 register bit 7 6 5 4 3 2 1 0 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs, or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim configuration option must have first enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via the sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0" rev. 1.50 166 march 06 , 2012 rev. 1.50 167 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro simc2 register bit 7 6 5 4 3 2 1 0 name d7 d6 ckpolb ckeg mls csen wcol trf r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 undefned bit this bit can be read or written by user software program. bit 5 ckpolb : determines the base condition of the clock line 0: the sck line will be high when the clock is inactive 1: the sck line will be low when the clock is inactive the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. bit 4 ckeg : determines spi sck active clock edge type ckpolb=0 0: sck is high base level and data capture at sck rising edge 1: sck is high base level and data capture at sck falling edge ckpolb=1 0: sck is low base level and data capture at sck falling edge 1: sck is low base level and data capture at sck rising edge the ckeg and ckpolb bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before data transfer is executed otherwise an erroneous clock edge may be generated. the ckpolb bit determines the base condition of the clock line, if the bit is high, then the sck line will be low when the clock is inactive. when the ckpolb bit is low, then the sck line will be high when the clock is inactive. the ckeg bit determines active clock edge type which depends upon the condition of ckpolb bit. bit 3 mls : spi data shift order 0: lsb 1: msb this is the data shift select bit and is used to select how the data is transferred, either msb or lsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 csen : spi scs pin control 0: disable 1: enable the csen bit is used as an enable/disable for the scs pin. if this bit is low, then the scs pin will be disabled and placed into a foating condition. if the bit is high the scs pin will be enabled and used as a select pin. note that using the csen bit can be disabled or enabled via confguration option. bit 1 wcol : spi write collision fag 0: no collision 1: collision the wcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the simd register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the wcol bit can be disabled or enabled via confguration option. bit 0 trf : spi transmit/receive complete fag 0: data is being transferred 1: spi data transmission is completed the trf bit is the transmit/receive complete fag and is set "1" automatically when an spi data transmission is completed, but must set to "0" by the application program. it can be used to generate an interrupt. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 166 march 06 , 2012 rev. 1.50 167 march 06 , 2012 spi communication after the spi interface is enabled by setting the simen bit high, then in the master mode, when data is written to the simd register, transmission/reception will begin simultaneously. when the data transfer is complete, the trf flag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the simd register will be transmitted and any data on the sdi pin will be shifted into the simd register. the master should output an scs signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scs signal depending upon the configurations of the ckpolb bit and ckeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the ckpolb and ckeg bits. the spi will continue to function even in the idle mode. ? ? ? ? ? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ?? ?? ? ?? ? ?? ?? -? ?? ?? ?? ?? ?? -? ?? ? ?? ?? ? ?? ? ? ? spi master mode timing ? ? ? ? ??? ? - ? ? ?? spi slave mode timing C ckeg=0 rev. 1.50 168 march 06 , 2012 rev. 1.50 169 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ? ??? ? ? ? ? ? ? ?? ?? ? - ? ?? ?? ? ? ?? ? ? ? ? ? ? ? ?? ?? ?? ? ? ?? ?? ??? ? ?? ? ? ? ? ? ? ?? spi slave mode timing C ckeg=1 ? ? ? ? ? ? ? ? ? ? ? - ? ?? ? ? ? ? ? ? ?? ?? ? ?? ? ??? ??? ? ?? ? ?? ?? ? spi transfer control flowchart ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 168 march 06 , 2012 rev. 1.50 169 march 06 , 2012 i 2 c interface the i 2 c interface is used to communicate with external peripheral devices such as sensors, eeprom memory etc. originally developed by philips, it is a two line low speed serial interface for synchronous serial data transfer. the advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. i 2 c master slave bus connection i 2 c interface operation the i 2 c serial interface is a two line interface, a serial data line, sda, and serial clock line, scl. as many devices may be connected together on the same bus, their outputs are both open drain types. for this reason it is necessary that external pull-high resistors are connected to these outputs. note that no chip select line exists, as each device on the i 2 c bus is identifed by a unique address which will be transmitted and received on the i 2 c bus. when two devices communicate with each other on the bidirectional i 2 c bus, one is known as the master device and one as the slave device. both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. for these devices, which only operates in slave mode, there are two methods of transferring data on the i 2 c bus, the slave transmit mode and the slave receive mode. there are several confguration options associated with the i 2 c interface. one of these is to enable the function which selects the sim pins rather than normal i/o pins. note that if the confguration option does not select the sim function then the simen bit in the simc0 register will have no effect. a confguration option exists to allow a clock other than the system clock to drive the i 2 c interface. another confguration option determines the debounce time of the i 2 c interface. this uses the internal clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. the debounce time, if selected, can be chosen to be either 1 or 2 system clocks. rev. 1.50 170 march 06 , 2012 rev. 1.50 171 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro i 2 c registers there are three control registers associated with the i 2 c bus, simc0, simc1 and sima and one data register, simd. the simd register, which is shown in the above spi section, is used to store the data being transmitted and received on the i 2 c bus. before the microcontroller writes data to the i 2 c bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the i 2 c bus, the microcontroller can read it from the simd register. any transmission or reception of data from the i 2 c bus must be made via the simd register. note that the sima register also has the name simc2 which is used by the spi function. bit simen and bits sim2~sim0 in register simc0 are used by the i 2 c interface. register name bit 7 6 5 4 3 2 1 0 simc0 sim2 sim1 sim0 pcken pckp1 pckp0 simen simc1 hcf haas hbb htx txak srw iamwu rxak simd d7 d6 d5 d4 d3 d2 d1 d0 sima iica6 iica5 iica4 iica3 iica2 iica1 iica0 d0 i 2 c registers list ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 170 march 06 , 2012 rev. 1.50 171 march 06 , 2012 simc0 register bit 7 6 5 4 3 2 1 0 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs, or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim configuration option must have first enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0" rev. 1.50 172 march 06 , 2012 rev. 1.50 173 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro simc0 register bit 7 6 5 4 3 2 1 0 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs, or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim configuration option must have first enabled the sim interface for this bit to be effective. if the sim is confgured to operate as an spi interface via sim2~sim0 bits, the contents of the spi control registers will remain at the previous settings when the simen bit changes from low to high and should therefore be frst initialised by the application program. if the sim is confgured to operate as an i 2 c interface via the sim2~sim0 bits and the simen bit changes from low to high, the contents of the i 2 c control bits such as htx and txak will remain at the previous settings and should therefore be first initialised by the application program while the relevant i 2 c flags such as hcf, haas, hbb, srw and rxak will be set to their default states. bit 0 unimplemented, read as "0" ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 172 march 06 , 2012 rev. 1.50 173 march 06 , 2012 simc1 register bit 7 6 5 4 3 2 1 0 name hcf haas hbb htx txak srw iamwu rxak r/w r r r r/w r/w r r/w r por 1 0 0 0 0 0 0 1 bit 7 hcf : i 2 c bus data transfer completion fag 0: data is being transferred 1: completion of an 8-bit data transfer the hcf flag is the data transfer flag. this flag will be zero when data is being transferred. upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. bit 6 haas : i 2 c bus address match fag 0: not address match 1: address match the hass fag is the address match fag. this fag is used to determine if the slave device address is the same as the master transmit address. if the addresses match then this bit will be high, if there is no match then the fag will be low . bit 5 hbb : i 2 c bus busy fag 0: i 2 c bus is not busy 1: i 2 c bus is busy the hbb flag is the i2c busy flag. this flag will be "1" when the i 2 c bus is busy which will occur when a start signal is detected. the fag will be set to "0" when the bus is free which will occur when a stop signal is detected. bit 4 htx : select i 2 c slave device is transmitter or receivera 0: slave device is the receiver 1: slave device is the transmitter bit 3 txak : i 2 c bus transmit acknowledge fag 0: slave send acknowledge fag 1: slave do not send acknowledge fag the txak bit is the transmit acknowledge fag. after the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. the slave device must always set txak bit to "0" before further data is received. bit 2 srw : i 2 c slave read/write fag 0: slave device should be in receive mode 1: slave device should be in transmit mode the srw flag is the i 2 c slave read/write flag. this flag determines whether the master device wishes to transmit or receive data from the i 2 c bus. when the transmitted address and slave address is match, that is when the haas fag is set high, the slave device will check the srw fag to determine whether it should be in transmit mode or receive mode. if the srw fag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. when the srw fag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. bit 1 iamwu : i 2 c address match wake-up control 0: disable 1: enable this bit should be set to "1" to enable i 2 c address match wake up from sleep or idle mode. bit 0 rxak : i 2 c bus receive acknowledge fag 0: slave receive acknowledge fag 1: slave do not receive acknowledge fag rev. 1.50 174 march 06 , 2012 rev. 1.50 175 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro the rxak flag is the receiver acknowledge flag. when the rxak flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. when the slave device in the transmit mode, the slave device checks the rxak fag to determine if the master receiver wishes to receive the next byte. the slave transmitter will therefore continue sending out data until the rxak fag is "1". when this occurs, the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the simd register is used to store the data being transmitted and received. the same register is used by both the spi and i 2 c functions. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the simd register. after the data is received from the spi bus, the device can read it from the simd register. any transmission or reception of data from the spi bus must be made via the simd register. simd register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x "x" unknown sima register bit 7 6 5 4 3 2 1 0 name iica6 iica5 iica4 iica3 iica2 iica1 iica0 r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x "x" unknown bit 7~1 iica6~ iica0 : i 2 c slave address iica6~ iica0 is the i 2 c slave address bit 6~ bit 0. the sima register is also used by the spi interface but has the name simc2. the sima register is the location where the 7-bit slave address of the slave device is stored. bits 7~ 1 of the sima register define the device slave address. bit 0 is not defned. when a master device, which is connected to the i 2 c bus, sends out an address, which matches the slave address in the sima register, the slave device will be selected. note that the sima register is the same register address as simc2 which is used by the spi interface. bit 0 undefned bit this bit can be read or written by user software program. ? ? ? ? ? ?- ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? i 2 c block diagram ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 174 march 06 , 2012 rev. 1.50 175 march 06 , 2012 i 2 c bus communication communication on the i 2 c bus requires four separate steps, a start signal, a slave device address transmission, a data transmission and fnally a stop signal. when a start signal is placed on the i 2 c bus, all devices on the bus will receive this signal and be notifed of the imminent arrival of data on the bus. the frst seven bits of the data will be the slave address with the frst bit being the msb. if the address of the slave device matches that of the transmitted address, the haas bit in the simc1 register will be set and an i 2 c interrupt will be generated. after entering the interrupt service routine, the slave device must frst check the condition of the haas bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. during a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the srw bit. this bit will be checked by the slave device to determine whether to go into transmit or receive mode. before any transfer of data to or from the i 2 c bus, the microcontroller must initialise the bus, the following are steps to achieve this: step 1 set the sim2~sim0 and simen bits in the simc0 register to "1" to enable the i 2 c bus. step 2 write the slave address of the device to the i 2 c bus address register sima. step 3 set the sime and sim muti-function interrupt enable bit of the interrupt control register to enable the sim interrupt and multi-function interrupt. ? ? ? ? ? ? - ? ? ? ? ? ?? ? ? ? ? ? - i 2 c bus initialisation flow chart rev. 1.50 176 march 06 , 2012 rev. 1.50 177 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro i 2 c bus start signal the start signal can only be generated by the master device connected to the i 2 c bus and not by the slave device. this start signal will be detected by all devices connected to the i 2 c bus. when detected, this indicates that the i 2 c bus is busy and therefore the hbb bit will be set. a start condition occurs when a high to low transition on the sda line takes place when the scl line remains high. slave address the transmission of a start signal by the master will be detected by all devices on the i 2 c bus. to determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the start signal. all slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. if the address sent out by the master matches the internal address of the microcontroller slave device, then an internal i 2 c bus interrupt signal will be generated. the next bit following the address, which is the 8th bit, defnes the read/write status and will be saved to the srw bit of the simc1 register. the slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. the slave device will also set the status fag haas when the addresses match. as an i 2 c bus interrupt can come from two sources, when the program enters the interrupt subroutine, the haas bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. i 2 c bus read/write signal the srw bit in the simc1 register defnes whether the slave device wishes to read data from the i 2 c bus or write data to the i 2 c bus. the slave device should examine this bit to determine if it is to be a transmitter or a receiver. if the srw fag is "1" then this indicates that the master device wishes to read data from the i 2 c bus, therefore the slave device must be setup to send data to the i 2 c bus as a transmitter. if the srw fag is "0" then this indicates that the master wishes to send data to the i 2 c bus, therefore the slave device must be setup to read data from the i 2 c bus as a receiver. i 2 c bus slave address acknowledge signal after the master has transmitted a calling address, any slave device on the i 2 c bus, whose own internal address matches the calling address, must generate an acknowledge signal. the acknowledge signal will inform the master that a slave device has accepted its calling address. if no acknowledge signal is received by the master then a stop signal must be transmitted by the master to end the communication. when the haas fag is high, the addresses have matched and the slave device must check the srw fag to determine if it is to be a transmitter or a receiver. if the srw fag is high, the slave device should be setup to be a transmitter so the htx bit in the simc1 register should be set to "1". if the srw fag is low, then the microcontroller slave device should be setup as a receiver and the htx bit in the simc1 register should be set to "0". ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 176 march 06 , 2012 rev. 1.50 177 march 06 , 2012 i 2 c bus data and acknowledge signal the transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. the order of serial bit transmission is the msb frst and the lsb last. after receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. if the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the sda line to allow the master to send a stop signal to release the i 2 c bus. the corresponding data will be stored in the simd register. if setup as a transmitter, the slave device must frst write the data to be transmitted into the simd register. if setup as a receiver, the slave device must read the transmitted data from the simd register. when the slave receiver receives the data byte, it must generate an acknowledge bit, known as txak, on the 9th clock. the slave device, which is setup as a transmitter will check the rxak bit in the simc1 register to determine if it is to send another data byte, if not then it will release the sda line and await the receipt of a stop signal from the master. i 2 c communication timing diagram ? ? ? ? ? ? ? ? - ? - ? ? note: *when a slave address is matched, the device must be placed in either the transmit mode and then write data to the simd register, or in the receive mode where it must implement a dummy read from the simd register to release the scl line. rev. 1.50 178 march 06 , 2012 rev. 1.50 179 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ? ? ? ? i 2 c bus isr flow chart serial interface C spia the devices contain an independent spi function. it is important not to confuse this independent spi function with the additional one contained within the combined sim function, which is described in another section of this datasheet. this independent spi function will carry the name spia to distinguish it from the other one in the sim. the spi interface is often used to communicate with external peripheral devices such as sensors, flash or eeprom memory devices etc. originally developed by motorola, the four line spi interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. the communication is full duplex and operates as a slave/master type, where the device can be either master or slave. although the spia interface specifcation can control multiple slave devices from a single master, however this device is provided with only one scsa pin. if the master needs to control multiple slave devices from a single master, the master can use i/o pins to select the slave devices. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 178 march 06 , 2012 rev. 1.50 179 march 06 , 2012 spia interface operation the spia interface is a full duplex synchronous serial data link. it is a four line interface with pin names sdia, sdoa, scka and scsa . pins sdia and sdoa are the serial data input and serial data output lines, scka is the serial clock line and scsa is the slave select line. as the spia interface pins are pin-shared with normal i/o pins, the spia interface must first be enabled by selecting the spia enable configuration option and setting the correct bits in the spiac0 and spiac1 registers. after the spia configuration option has been configured it can also be additionally disabled or enabled using the spiaen bit in the spiac0 register. communication between devices connected to the spia interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. the master also controls the clock signal. as the device only contains a single scsa pin only one slave device can be utilized. the scsa pin is controlled by the application program, set the sacsen bit to 1 to enable the scsa pin function and clear the sacsen bit to 0 to place the scsa pin into a foating state. spia master/slave connection ? ? ? ? ? ? ? ? ? ? - ? ? ? ? ? ? ? ? ? ? ? ? spia block diagram the spia function in this device offers the following features: full duplex synchronous data transfer both master and slave modes lsb frst or msb frst data transmission modes transmission complete fag rising or falling active clock edge sawcol and sacsen bit enabled or disable select the status of the spia interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as sacsen and spiaen. rev. 1.50 180 march 06 , 2012 rev. 1.50 181 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro there are several confguration options associated with the spia interface. one of these is to enable the spia function which selects the spia pins rather than normal i/o pins. note that if the confguration option does not select the spia function then the spiaen bit in the spiac0 register will have no effect. another two spia configuration options determine if the sacsen and sawcol bits are to be used. spia registers there are three internal registers which control the overall operation of the spia interface. these are the spiad data register and two registers spiac0 and spiac1. register name bit 7 6 5 4 3 2 1 0 spiac0 saspi2 saspi1 saspi0 spiaen spiac1 sackpol sackeg samls sacsen sawcol satrf spiad d7 d6 d5 d4 d3 d2 d1 d0 spia registers list the spiad register is used to store the data being transmitted and received. before the device writes data to the spi bus, the actual data to be transmitted must be placed in the spiad register. after the data is received from the spi bus, the device can read it from the spiad register. any transmission or reception of data from the spi bus must be made via the spiad register. spi a d register bit 7 6 5 4 3 2 1 0 name d7 d6 d5 d4 d3 d2 d1 d0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por x x x x x x x x x unknown there are also two control registers for the spia interface, spiac0 and spiac1. register spiac0 is used to control the enable/disable function and to set the data transmission clock frequency. register spiac1 is used for other control functions such as lsb/msb selection, write collision fag etc. spiac0 register bit 7 6 5 4 3 2 1 0 name saspi2 saspi1 saspi0 spiaen r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 0 bit 7~5 saspi2~saspi0 : master/slave clock select 000 : spia master, f sys /4 001 : spia master, f sys /16 010 : spia master, f sys /64 011 : spia master, f sub 100 : spia master, tp0 ccrp match frequency/2 (pfd) 101 : spia slave bit 4~2 unimplemented, read as 0 bit 1 spiaen : spia enable or disable 0: disable 1: enable bit 0 unimplemented, read as 0 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 180 march 06 , 2012 rev. 1.50 181 march 06 , 2012 spiac1 register bit 7 6 5 4 3 2 1 0 name sackpol sackeg samls sacsen sawcol satrf r/w r r r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 unimp lemented, read as 0. this bit can be read or written by user software program. bit 5 sackpol : determines the base condition of the clock line 0: scka line will be high when the clock is inactive 1: scka line will be low when the clock is inactive the sackpol bit determines the base condition of the clock line, if the bit is high, then the scka line will be low when the clock is inactive. when the sackpol bit is low, then the scka line will be high when the clock is inactive. bit 4 sackeg : determines the spia scka active clock edge type sackpol = 0: 0: scka has high base level with data capture on scka rising edge 1: scka has high base level with data capture on scka falling edge sackpol = 1: 0: scka has low base level with data capture on scka falling edge 1: scka has low base level with data capture on scka rising edge the sackeg and sackpol bits are used to setup the way that the clock signal outputs and inputs data on the spi bus. these two bits must be confgured before a data transfer is executed otherwise an erroneous clock edge may be generated. the sackpol bit determines the base condition of the clock line, if the bit is high, then the scka line will be low when the clock is inactive. when the sackpol bit is low, then the scka line will be high when the clock is inactive. the sackeg bit determines active clock edge type which depends upon the condition of the sackpol bit. bit 3 samls : msb/lsb first bit 0: lsb shift frst 1: msb shift frst this is the data shift select bit and is used to select how the data is transferred, either msb orlsb frst. setting the bit high will select msb frst and low for lsb frst. bit 2 sacsen : select signal enable/disable bit 0: scsa foating 1: enable the sacsen bit is used as an enable/disable for the scs a pin. if this bit is low, then the scsa pin will be disabled and placed into a foating condition. if the bit is high the scsa pin will be enabled and used as a select pin. note that using the sacsen bit can be disabled or enabled via confguration option. bit 1 sawcol : write collision bit 0: collision free 1: collision detected the sawcol fag is used to detect if a data collision has occurred. if this bit is high it means that data has been attempted to be written to the spiad register during a data transfer operation. this writing operation will be ignored if data is being transferred. the bit can be cleared by the application program. note that using the sawcol bit can be disabled or enabled via confguration option. bit 0 satrf : transmit /receive flag 0: not complete 1: transmission/reception complete the satrf bit is the transmit/receive complete flag and is set 1 automatically when an spia data transmission is completed, but must set to zero by the application program. it can be used to generate an interrupt. rev. 1.50 182 march 06 , 2012 rev. 1.50 183 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro spia communication after the spia interface is enabled by setting the spiaen bit high, then in the master mode, when data is written to the spiad register, transmission/reception will begin simultaneously. when the data transfer is complete, the satrf fag will be set automatically, but must be cleared using the application program. in the slave mode, when the clock signal from the master has been received, any data in the spiad register will be transmitted and any data on the sdia pin will be shifted into the spiad register. the master should output an scsa signal to enable the slave device before a clock signal is provided. the slave data to be transferred should be well prepared at the appropriate moment relative to the scsa signal depending upon the confgurations of the sackpol bit and sackeg bit. the accompanying timing diagram shows the relationship between the slave data and scs signal for various confgurations of the sackpol and sackeg bits. the spia will continue to function even in the idle mode. ? ?? ?? ?? ? -? ? ?? - ?? ? ? ? ? ? ?? ?? ?? ? -? ? ?? - ?? ? ? ? ? ? ? ? spia master mode timing ? ? ? ??? ? ? - ? ? spia slave mode timing C sackeg=0 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 182 march 06 , 2012 rev. 1.50 183 march 06 , 2012 ? ? ? ? ? ? ? -? ? ? ? ? ? ? ? ? ?? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? spia slave mode timing C sackeg=1 ? ? ? ? ? ? ? ? ? ? ? ? - ? ? ? ? ?? ? ? ?? ?? ? ???? ??? ??? ? ?? ?? ?? ? ? spia transfer control flowchart rev. 1.50 184 march 06 , 2012 rev. 1.50 185 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro peripheral clock output the peripheral clock output allows the device to supply external hardware with a clock signal synchronised to the microcontroller clock. peripheral clock operation as the peripheral clock output pin, pck, is shared with i/o line, the required pin function is chosen via pcken in the simc0 register. the peripheral clock function is controlled using the simc0 register. the clock source for the peripheral clock output can originate from either the tm0 ccrp match frequency/2 or a divided ratio of the internal f sys clock. the pcken bit in the simc0 register is the overall on/off control, setting pcken bit to "1" enables the peripheral clock, setting pcken bit to "0" disables it. the required division ratio of the system clock is selected using the pckp1 and pckp0 bits in the same register. if the device enters the sleep mode this will disable the peripheral clock output. simc0 register bit 7 6 5 4 3 2 1 0 name sim2 sim1 sim0 pcken pckp1 pckp0 simen r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 0 0 0 0 bit 7~5 sim2, sim1, sim0 : sim operating mode control 000: spi master mode; spi clock is f sys /4 001: spi master mode; spi clock is f sys /16 010: spi master mode; spi clock is f sys /64 011: spi master mode; spi clock is f tbc 100: spi master mode; spi clock is tm0 ccrp match frequency/2 101: spi slave mode 110: i 2 c slave mode 111: unused mode these bits setup the overall operating mode of the sim function. as well as selecting if the i 2 c or spi function, they are used to control the spi master/slave selection and the spi master clock frequency. the spi clock is a function of the system clock but can also be chosen to be sourced from the tm0. if the spi slave mode is selected then the clock will be supplied by an external master device. bit 4 pcken : pck output pin control 0: disable 1: enable bit 3~2 pckp1, pckp0 : select pck output pin frequency 00: f sys 01: f sys /4 10: f sys /8 11: tm0 ccrp match frequency/2 bit 1 simen : sim control 0: disable 1: enable the bit is the overall on/off control for the sim interface. when the simen bit is cleared to zero to disable the sim interface, the sdi, sdo, sck and scs , or sda and scl lines will be in a foating condition and the sim operating current will be reduced to a minimum value. when the bit is high the sim interface is enabled. the sim configuration option must have first enabled the sim interface for this bit to be effective. note that when the simen bit changes from low to high the contents of the spi control registers will be in an unknown condition and should therefore be first initialised by the application program. bit 0 unimplemented, read as "0" ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 184 march 06 , 2012 rev. 1.50 185 march 06 , 2012 interrupts interrupts are an important part of any microcontroller system. when an external event or an internal function such as a timer module or an a/d converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. the device contains several external interrupt and internal interrupts functions. the external interrupts are generated by the action of the external int0~int3 and pint pins, while the internal interrupts are generated by various internal functions such as the tms, comparators, time base, lvd, eeprom, sim, spia and the a/d converter. interrupt registers overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the special purpose data memory, as shown in the accompanying table. the number of registers depends upon the device chosen but fall into three categories. the frst is the intc0~intc3 registers which setup the primary interrupts, the second is the mfi0~mfi3 registers which setup the multi-function interrupts. finally there is an integ register to setup the external interrupt trigger edge type. each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. the naming convention of these follows a specifc pattern. first is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an e for enable/disable bit or f for request fag. function enable bit request flag notes global emi comparator cpne cpnf n = 0 or 1 intn pin intne intnf n = 0~3 a/d converter ade adf multi-function mfne mfnf n = 0~5 time base tbne tbnf n = 0 or 1 sim sime simf spia spiae spiaf lvd lve lvf eeprom dee def pint pin xpe xpf tm tnpe tnpf n = 0~3 tnae tnaf tnbe tnbf interrupt register bit naming conventions rev. 1.50 186 march 06 , 2012 rev. 1.50 187 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro interrupt register contents ht67f30 name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e emi intc1 adf mf1f mf0f cp1f ade mf1e mf0e cp1e intc2 mf3f tb1f tb0f mf2f mf3e tb1e tb0e mf2e mfi0 t0af t0pf t0ae t0pe mfi1 t1bf t1af t1pf t1be t1ae t1pe mfi2 xpf simf xpe sime mfi3 spiaf def lvf spiae dee lve ht67f40 name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e emi intc1 adf mf1f mf0f cp1f ade mf1e mf0e cp1e intc2 mf3f tb1f tb0f mf2f mf3e tb1e tb0e mf2e mfi0 t2af t2pf t0af t0pf t2ae t2pe t0ae t0pe mfi1 t1bf t1af t1pf t1be t1ae t1pe mfi2 xpf simf xpe sime mfi3 spiaf def lvf spiae dee lve HT67F50 name bit 7 6 5 4 3 2 1 0 integ int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e emi intc1 adf mf1f mf0f cp1f ade mf1e mf0e cp1e intc2 mf3f tb1f tb0f mf2f mf3e tb1e tb0e mf2e mfi0 t2af t2pf t0af t0pf t2ae t2pe t0ae t0pe mfi1 t1bf t1af t1pf t1be t1ae t1pe mfi2 t3af t3pf xpf simf t3ae t3pe xpe sime mfi3 spiaf def lvf spiae dee lve ht67f60 name bit 7 6 5 4 3 2 1 0 integ int3s1 int3s0 int2s1 int2s0 int1s1 int1s0 int0s1 int0s0 intc0 cp0f int1f int0f cp0e int1e int0e emi intc1 adf mf1f mf0f cp1f ade mf1e mf0e cp1e intc2 mf3f tb1f tb0f mf2f mf3e tb1e tb0e mf2e intc3 int3f int2f int3e int2e mfi0 t2af t2pf t0af t0pf t2ae t2pe t0ae t0pe mfi1 t1bf t1af t1pf t1be t1ae t1pe mfi2 t3af t3pf xpf simf t3ae t3pe xpe sime mfi3 spiaf def lvf spiae dee lve ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 186 march 06 , 2012 rev. 1.50 187 march 06 , 2012 integ register ht67f30/ht67f40/HT67F50 bit 7 6 5 4 3 2 1 0 name int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~4 unimplemented, read as "0" bit 3~2 int1s1, int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges ht67f60 bit 7 6 5 4 3 2 1 0 name int3s1 int3s0 int2s1 int2s0 int1s1 int1s0 int0s1 int0s0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7~6 int3s1, int3s0 : interrupt edge control for int3 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 5~4 int2s1, int2s0 : interrupt edge control for int2 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 3~2 int1s1, int1s0 : interrupt edge control for int1 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges bit 1~0 int0s1, int0s0 : interrupt edge control for int0 pin 00: disable 01: rising edge 10: falling edge 11: rising and falling edges rev. 1.50 188 march 06 , 2012 rev. 1.50 189 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro intc0 register ht67f30/ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name cp0f int1f int0f cp0e int1e int0e emi r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 cp0f : comparator 0 interrupt request fag 0: no request 1: interrupt request bit 5 int1f : int1 interrupt request fag 0: no request 1: interrupt request bit 4 int0f : int0 interrupt request fag 0: no request 1: interrupt request bit 3 cp0e : comparator 0 interrupt control 0: disable 1: enable bit 2 int1e : int1 interrupt control 0: disable 1: enable bit 1 int0e : int0 interrupt control 0: disable 1: enable bit 0 emi : global interrupt control 0: disable 1: enable intc1 register ht67f30/ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name adf mf1f mf0f cp1f ade mf1e mf0e cp1e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 adf : a/d converter interrupt request flag 0: no request 1: interrupt request bit 6 mf1f : multi-function interrupt 1 request flag 0: no request 1: interrupt request bit 5 mf0f : multi-function interrupt 0 request flag 0: no request 1: interrupt request bit 4 cp1f : comparator 1 interrupt request flag 0: no request 1: interrupt request bit 3 ade : a/d converter interrupt control 0: disable 1: enable bit 2 mf1e : multi-function interrupt 1 control 0: disable 1: enable bit 1 mf0e : multi-function interrupt 0 control 0: disable 1: enable bit 0 cp1e : comparator 1 interrupt control 0: disable 1: enable ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 188 march 06 , 2012 rev. 1.50 189 march 06 , 2012 intc2 register ht67f30/ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name mf3f tb1f tb0f mf2f mf3e tb1e tb0e mf2e r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 mf3f : multi-function interrupt 3 request flag 0: no request 1: interrupt request bit 6 tb1f : time base 1 interrupt request flag 0: no request 1: interrupt request bit 5 tb0f : time base 0 iinterrupt request flag 0: no request 1: interrupt request bit 4 mf2f : multi-function interrupt 2 request flag 0: no request 1: interrupt request bit 3 mf3e : multi-function interrupt 3 control 0: disable 1: enable bit 2 tb1e : time base 1 interrupt control 0: disable 1: enable bit 1 tb0e : time base 0 interrupt control 0: disable 1: enable bit 0 mf2e : multi-function interrupt 2 control 0: disable 1: enable intc3 register ht67f60 bit 7 6 5 4 3 2 1 0 name int3f int2f int3e int2e r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 int3f : int3 interrupt request fag 0: no request 1: interrupt request bit 4 int2f : int2 interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 int3e : int3 interrupt control 0: disable 1: enable bit 0 int2e : int2 interrupt control 0: disable 1: enable rev. 1.50 190 march 06 , 2012 rev. 1.50 191 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro mfi0 register ht67f30 bit 7 6 5 4 3 2 1 0 name t0af t0pf t0ae t0pe r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name t2af t2pf t0af t0pf t2ae t2pe t0ae t0pe r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t2af : tm2 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t2pf : tm2 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 t0af : tm0 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t0pf : tm0 comparator p match interrupt request fag 0: no request 1: interrupt request bit 3 t2ae : tm2 comparator a match interrupt control 0: disable 1: enable bit 2 t2pe : tm2 comparator p match interrupt control 0: disable 1: enable bit 1 t0ae : tm0 comparator a match interrupt control 0: disable 1: enable bit 0 t0pe : tm0 comparator p match interrupt control 0: disable 1: enable ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 190 march 06 , 2012 rev. 1.50 191 march 06 , 2012 mfi1 register ht67f30/ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name t1bf t1af t1pf t1be t1ae t1pe r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 t1bf : tm1 comparator b match interrupt request fag 0: no request 1: interrupt request bit 5 t1af : tm1 comparator a match interrupt request fag 0: no request 1: interrupt request bit 4 t1pf : tm1 comparator b match interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as "0" bit 2 t1be : tm1 comparator p match interrupt control 0: disable 1: enable bit 1 t1ae : tm1 comparator a match interrupt control 0: disable 1: enable bit 0 t1pe : tm1 comparator p match interrupt control 0: disable 1: enable mfi2 register ht67f30/ht67f40 bit 7 6 5 4 3 2 1 0 name xpf simf xpe sime r/w r/w r/w r/w r/w por 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 xpf : external peripheral interrupt request fag 0: no request 1: interrupt request bit 4 simf : sim interrupt request fag 0: no request 1: interrupt request bit 3~2 unimplemented, read as "0" bit 1 xpe : external peripheral interrupt control 0: disable 1: enable bit 0 sime : sim interrupt control 0: disable 1: enable rev. 1.50 192 march 06 , 2012 rev. 1.50 193 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name t3af t3pf xpf simf t3ae t3pe xpe sime r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 0 bit 7 t3af : tm3 comparator a match interrupt request fag 0: no request 1: interrupt request bit 6 t3pf : tm3 comparator p match interrupt request fag 0: no request 1: interrupt request bit 5 xpf : external peripheral interrupt request fag 0: no request 1: interrupt request bit 4 simf : sim interrupt request fag 0: no request 1: interrupt request bit 3 t3ae : tm3 comparator a match interrupt control 0: disable 1: enable bit 2 t3pe : tm3 comparator p match interrupt control 0: disable 1: enable bit 1 xpe : external peripheral interrupt control 0: disable 1: enable bit 0 sime : sim interrupt control 0: disable 1: enable mfi3 register ht67f30/ht67f40/HT67F50/ht67f60 bit 7 6 5 4 3 2 1 0 name spiaf def lvf spiae dee lve r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 bit 7 unimplemented, read as "0" bit 6 spiaf : spia interrupt request fag 0: no request 1: interrupt request bit 5 def : data eeprom interrupt request fag 0: no request 1: interrupt request bit 4 lvf : lvd interrupt request fag 0: no request 1: interrupt request bit 3 unimplemented, read as "0" bit 2 spiae : spia interrupt control 0: disable 1: enable bit 1 dee : data eeprom interrupt control 0: disable 1: enable bit 0 lve : lvd interrupt control 0: disable 1: enable ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 192 march 06 , 2012 rev. 1.50 193 march 06 , 2012 interrupt operation when the conditions for an interrupt event occur, such as a tm comparator p, comparator a or comparator b match or a/d conversion completion etc, the relevant interrupt request fag will be set. whether the request fag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. if the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request fag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. the global interrupt enable bit, if cleared to zero, will disable all interrupts. when an interrupt is generated, the program counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. the program counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. the microcontroller will then fetch its next instruction from this interrupt vector. the instruction at this vector will usually be a jmp which will jump to another section of program which is known as the interrupt service routine. here is located the code to control the appropriate interrupt. the interrupt service routine must be terminated with a "reti" , which retrieves the original program counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. the various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, emi bit will be cleared automatically. this will prevent any further interrupt nesting from occurring. however, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request fag will still be recorded. if an interrupt requires immediate servicing while the program is already in another interrupt service routine, the emi bit should be set after entering the routine, to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the stack pointer is decremented. if immediate service is desired, the stack must be prevented from becoming full. in case of simultaneous requests, the accompanying diagram shows the priority that is applied. all of the interrupt request fags when set will wake-up the device if it is in sleep or idle mode, however to prevent a wake-up from occurring the corresponding fag should be set before the device is in sleep or idle mode. rev. 1.50 194 march 06 , 2012 rev. 1.50 195 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro 04h 08h 0ch 10h 14h 18h 1ch 20h 24h 28h vector low priority high request flags enable bits master enable request flags enable bits emi auto disabled in isr interrupts contained within multi - function interrupts interrupt name interrupt name mf3f m. funct . 3 mf3e xpf pint pin xpe emi 2ch lvf lvd lve def eeprom dee emi emi emi emi emi emi emi emi emi simf sim sime t1bf tm1 b t1be t1af tm1 a t1ae t1pf tm1 p t1pe t0af tm0 a t0ae t0pf tm0 p t0pe int0f int0 pin int0e int1f int1 pin int1e cp0f comp. 0 cp0e cp1f comp. 1 cp1e mf0f m. funct . 0 mf0e mf1f m. funct . 1 mf1e adf a/d ade emi mf2f m. funct . 2 mf2e tb0f time base 0 tb0e tb1f time base 1 tb1e xxf legend request flag C no auto reset in isr xxf request flag C auto reset in isr xxe enable bit spiaf spia espia interrupt structure C ht67f30 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 194 march 06 , 2012 rev. 1.50 195 march 06 , 2012 04h 0ch 14h 18h 1ch 20h 24h 28h request flags enable bits interrupts contained within multi - function interrupts interrupt name mf3f m. funct . 3 mf3e xpf pint pin xpe emi lvf lvd lve def eeprom dee emi emi emi emi emi emi emi emi emi simf sim sime t1bf tm1 b t1be t1af tm1 a t1ae t1pf tm1 p t1pe tp0af tm0 a t0ae tp0af tm0 p t0pe int0f int0 pin int0e int1f int1 pin int1e cp0f comp. 0 cp0e cp1f comp. 1 cp1e mf0f m. funct . 0 mf0e mf1f m. funct . 1 mf1e adf a/d ade emi mf2f m. funct . 2 mf2e tb0f time base 0 tb0e tb1f time base 1 tb1e t2af tm2 a t2ae t2pf tm2 p t2pe t3af tm3 a t3ae t3pf tm3 p t3pe HT67F50 only low priority high xxf legend request flag C no auto reset in isr xxf request flag C auto reset in isr xxe enable bit vector request flags enable bits master enable emi auto disabled in isr interrupt name 08h 2ch 10h spiaf spia espia interrupt structure C ht67f40/HT67F50 rev. 1.50 196 march 06 , 2012 rev. 1.50 197 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro 14h request flags enable bits interrupt name xxf legend request flag C no auto reset in isr xxf request flag C auto reset in isr xxe enable bit xxf legend request flag C no auto reset in isr xxf request flag C auto reset in isr xxe enable bit emi auto disabled in isr emi auto disabled in isr simf sim simf sim sime t1pf tm1 p t1pe t2af tm2 a t2ae t2pf tm2 p t2pe t0af tm0 a t0ae t0pf tm0 p t0pe emi mf0f m. funct . 0 mf0e emi mf0f m. funct . 0 mf0e 18h emi mf1f m. funct . 1 mf1e 18h emi mf1f m. funct . 1 mf1e 18h emi mf1f m. funct . 1 mf1f m. funct . 1 mf1e t3pf tm3 p t3pe t3af tm3 a t3ae t3af tm3 a t3ae low priority high vector 04h 08h 0ch 10h emi emi emi emi int0f int0 pin int0e int1f int1 pin int1e cp0f comp. 0 cp0e cp1f comp. 1 cp1e request flags enable bits master enable interrupt name 04h 08h 0ch 10h emi emi emi emi int0f int0 pin int0e int1f int1 pin int1e cp0f comp. 0 cp0e cp1f comp. 1 cp1e request flags enable bits master enable interrupt name emi emi emi emi int0f int0 pin int0e int1f int1 pin int1e cp0f comp. 0 cp0e cp1f comp. 1 cp1e request flags enable bits master enable interrupt name xpe xpf pint pin interrupts contained within multi - function interrupts t1af tm1 a t1ae t1af tm1 a t1ae t1bf tm1 b t1be t1bf tm1 b t1be adf a/d ade emi 1ch adf a/d ade emi 1ch 20h emi mf2f m. funct . 2 mf2e 20h emi mf2f m. funct . 2 mf2e 20h emi mf2f m. funct . 2 mf2f m. funct . 2 mf2e emi tb0f time base 0 tb0e 24h emi tb1f time base 1 tb1e 28h emi tb0f time base 0 tb0e 24h emi tb1f time base 1 tb1f time base 1 tb1e 28h lvf lvd lve def eeprom dee def eeprom dee spiaf spia espia spiaf spia espia 2ch emi mf3f m. funct . 3 mf3e 2ch emi mf3f m. funct . 3 mf3e 2ch emi mf3f m. funct . 3 mf3f m. funct . 3 mf3e 30h emi int2f int2 pin int2e 30h emi int2f int2 pin int2f int2 pin int2e 34h emi int3f int3 pin int3e 34h emi int3f int3 pin int3f int3 pin int3e interrupt structure C ht67f60 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 196 march 06 , 2012 rev. 1.50 197 march 06 , 2012 external interrupt the external interrupts are controlled by signal transitions on the pins int0~int3. an external interrupt request will take place when the external interrupt request fags, int0f~int3f, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and respective external interrupt enable bit, int0e~int3e, must frst be set. additionally the correct interrupt edge type must be selected using the integ register to enable the external interrupt function and to choose the trigger edge type. as the external interrupt pins are pin-shared with i/o pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. the pin must also be setup as an input by setting the corresponding bit in the port control register. when the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, int0f~int3f, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. the integ register is used to select the type of active edge that will trigger the external interrupt. a choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. note that the integ register can also be used to disable the external interrupt function. comparator interrupt the comparator interrupt is controlled by the two internal comparators. a comparator interrupt request will take place when the comparator interrupt request flags, cp0f or cp1f, are set, a situation that will occur when the comparator output changes state. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and comparator interrupt enable bits, cp0e and cp1e, must frst be set. when the interrupt is enabled, the stack is not full and the comparator inputs generate a comparator output transition, a subroutine call to the comparator interrupt vector, will take place. when the interrupt is serviced, the external interrupt request fags, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. multi-function interrupt within these devices there are up to four multi-function interrupts. unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the tm interrupts, sim interrupt, spia interrupt, external peripheral interrupt, lvd interrupt and eeprom interrupt. a multi-function interrupt request will take place when any of the multi-function interrupt request fags, mf0f~mf3f are set. the multi-function interrupt fags will be set when any of their included functions generate an interrupt request flag. to allow the program to branch to its respective interrupt vector address, when the multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of multi-function interrupt occurs, a subroutine call to one of the multi-function interrupt vectors will take place. when the interrupt is serviced, the related multi-function request fag, will be automatically reset and the emi bit will be automatically cleared to disable other interrupts. rev. 1.50 198 march 06 , 2012 rev. 1.50 199 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro however, it must be noted that, although the multi-function interrupt fags will be automatically reset when the interrupt is serviced, the request fags from the original source of the multi-function interrupts, namely the tm interrupts, sim interrupt, spia interrupt, external peripheral interrupt, lvd interrupt and eeprom interrupt will not be automatically reset and must be manually reset by the application program. a/d converter interrupt the a/d converter interrupt is controlled by the termination of an a/d conversion process. an a/d converter interrupt request will take place when the a/d converter interrupt request fag, adf, is set, which occurs when the a/d conversion process fnishes. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and a/d interrupt enable bit, ade, must first be set. when the interrupt is enabled, the stack is not full and the a/d conversion process has ended, a subroutine call to the a/d converter interrupt vector, will take place. when the interrupt is serviced, the a/d converter interrupt fag, adf, will be automatically cleared. the emi bit will also be automatically cleared to disable other interrupts. time base interrupts the function of the time base interrupts is to provide regular time signal in the form of an internal interrupt. they are controlled by the overfow signals from their respective timer functions. when these happens their respective interrupt request fags, tb0f or tb1f will be set. to allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, emi and time base enable bits, tb0e or tb1e, must frst be set. when the interrupt is enabled, the stack is not full and the time base overfows, a subroutine call to their respective vector locations will take place. when the interrupt is serviced, the respective interrupt request fag, tb0f or tb1f, will be automatically reset and the emi bit will be cleared to disable other interrupts. the purpose of the time base interrupt is to provide an interrupt signal at fxed time periods. their clock sources originate from the internal clock source f tb . this f tb input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the tbc register to obtain longer interrupt periods whose value ranges. the clock source that generates f tb , which in turn controls the time base interrupt period, can originate from several different sources, as shown in the system operating mode section. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 198 march 06 , 2012 rev. 1.50 199 march 06 , 2012 tbc register bit 7 6 5 4 3 2 1 0 name tbon tbck tb11 tb10 lxtlp tb02 tb01 tb00 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 1 1 0 1 1 1 bit 7 tbon : tb0 and tb1 control 0: disable 1: enable bit 6 tbck : select f tb clock 0: f tbc 1: f sys /4 bit 5~4 tb11~tb10 : select time base 1 time-out period 00: 4096/f tb 01: 8192/f tb 10: 16384/f tb 11: 32768/f tb bit 3 lxtlp : lxt low power control 0: disable 1: enable bit 2~0 tb02~tb00 : select time base 0 time-out period 000: 256/f tb 001: 512/f tb 010: 1024/f tb 011: 2048/f tb 100: 4096/f tb 101: 8192/f tb 110: 16384/f tb 111: 32768/f tb ? ? ? time base interrupt rev. 1.50 200 march 06 , 2012 rev. 1.50 201 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro serial interface module interrupt the serial interface module interrupt, also known as the sim interrupt, is contained within the multi-function interrupt. a sim interrupt request will take place when the sim interrupt request fag, simf, is set, which occurs when a byte of data has been received or transmitted by the sim interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, sime, and muti-function interrupt enable bits, must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the sim interface, a subroutine call to the respective multi-function interrupt vector, will take place. when the serial interface interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the simf fag will not be automatically cleared, it has to be cleared by the application program. external peripheral interrupt the external peripheral interrupt operates in a similar way to the external interrupt and is contained within the multi-function interrupt. a peripheral interrupt request will take place when the external peripheral interrupt request fag, xpf, is set, which occurs when a negative edge transition appears on the pint pin. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, external peripheral interrupt enable bit, xpe, and associated multi- function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a negative transition appears on the external peripheral interrupt pin, a subroutine call to the respective multi-function interrupt, will take place. when the external peripheral interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the xpf fag will not be automatically cleared, it has to be cleared by the application program. the external peripheral interrupt pin is pin-shared with several other pins with different functions. it must therefore be properly confgured to enable it to operate as an external peripheral interrupt pin. serial interface interrupt the serial interface interrupt, also known as the spia interrupt, is contained within the multi- function interrupt. a spia interrupt request will take place when the spia interrupt request fag, spiaf, is set, which occurs when a byte of data has been received or transmitted by the spia interface. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, and the serial interface interrupt enable bit, spiae, and multi-function interrupt enable bits, must frst be set. when the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the spia interface, a subroutine call to the respective multi-function interrupt vector, will take place. when the serial interface interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the spiaf fag will not be automatically cleared, it has to be cleared by the application program. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 200 march 06 , 2012 rev. 1.50 201 march 06 , 2012 eeprom interrupt the eeprom interrupt, is contained within the multi-function interrupt. an eeprom interrupt request will take place when the eeprom interrupt request fag, def, is set, which occurs when an eeprom write cycle ends. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, eeprom interrupt enable bit, dee, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and an eeprom write cycle ends, a subroutine call to the respective multi-function interrupt vector, will take place. when the eeprom interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the def fag will not be automatically cleared, it has to be cleared by the application program. lvd interrupt the low voltage detector interrupt is contained within the multi-function interrupt. an lvd interrupt request will take place when the lvd interrupt request flag, lvf, is set, which occurs when the low voltage detector function detects a low power supply voltage. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, low voltage interrupt enable bit, lve, and associated multi-function interrupt enable bit, must frst be set. when the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the multi-function interrupt vector, will take place. when the low voltage interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the multi-function interrupt request fag will be also automatically cleared. as the lvf fag will not be automatically cleared, it has to be cleared by the application program. tm interrupts the compact and standard type tms have two interrupts each, while the enhanced type tm has three interrupts. all of the tm interrupts are contained within the multi-function interrupts. for each of the compact and standard type tms there are two interrupt request fags tnpf and tnaf and two enable bits tnpe and tnae. for the enhanced type tm there are three interrupt request fags tnpf, tnaf and tnbf and three enable bits tnpe, tnae and tnbe. a tm interrupt request will take place when any of the tm request fags are set, a situation which occurs when a tm comparator p, a or b match situation happens. to allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, emi, respective tm interrupt enable bit, and relevant multi-function interrupt enable bit, mfne, must frst be set. when the interrupt is enabled, the stack is not full and a tm comparator match situation occurs, a subroutine call to the relevant multi-function interrupt vector locations, will take place. when the tm interrupt is serviced, the emi bit will be automatically cleared to disable other interrupts, however only the related mfnf fag will be automatically cleared. as the tm interrupt request fags will not be automatically cleared, they have to be cleared by the application program. rev. 1.50 202 march 06 , 2012 rev. 1.50 203 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro interrupt wake-up function each of the interrupt functions has the capability of waking up the microcontroller when in the sleep or idle mode. a wake-up is generated when an interrupt request fag changes from low to high and is independent of whether the interrupt is enabled or not. therefore, even though the device is in the sleep or idle mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt fag to be set high and consequently generate an interrupt. care must therefore be taken if spurious wake-up situations are to be avoided. if an interrupt wake-up function is to be disabled then the corresponding interrupt request fag should be set high before the device enters the sleep or idle mode. the interrupt enable bits have no effect on the interrupt wake-up function. programming considerations by disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request fag is cleared by the application program. where a certain interrupt is contained within a multi-function interrupt, then when the interrupt service routine is executed, as only the multi-function interrupt request fags, mf0f~mf3f, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. it is recommended that programs do not use the call instruction within the interrupt service subroutine. interrupts often occur in an unpredictable manner or need to be serviced immediately. if only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a call subroutine is executed in the interrupt subroutine. every interrupt has the capability of waking up the microcontroller when it is in sleep or idle mode, the wake up being generated when the interrupt request fag changes from low to high. if it is required to prevent a certain interrupt from waking up the microcontroller then its respective request fag should be frst set high before enter sleep or idle mode. as only the program counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. to return from an interrupt subroutine, either a ret or reti instruction may be executed. the reti instruction in addition to executing a return to the main program also automatically sets the emi bit high to allow further interrupts. the ret instruction however only executes a return to the main program leaving the emi bit in its present zero state and therefore disabling the execution of further interrupts. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 202 march 06 , 2012 rev. 1.50 203 march 06 , 2012 power down mode and wake-up entering the idle or sleep mode there is only one way for the device to enter the sleep or idle mode and that is to execute the "halt" instruction in the application program. when this instruction is executed, the following will occur: the system clock will be stopped and the application program will stop at the "halt" instruction. the data memory contents and registers will maintain their present condition. the wdt will be cleared and resume counting if the wdt clock source is selected to come from the f sub clock source and the wdt is enabled. the wdt will stop if its clock source originates from the system clock. the i/o ports will maintain their present condition. in the status register, the power down fag, pdf, will be set and the watchdog time-out fag, to, will be cleared. standby current considerations as the main reason for entering the sleep or idle mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. special attention must be made to the i/o pins on the device. all high-impedance input pins must be connected to either a fxed high or low level as any foating input pins could create internal oscillations and result in increased current consumption. this also applies to devices which have different package types, as there may be unbonbed pins. these must either be setup as outputs or if setup as inputs must have pull-high resistors connected. care must also be taken with the loads, which are connected to i/o pins, which are setup as outputs. these should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other cmos inputs. also note that additional standby current will also be required if the confguration options have enabled the lirc oscillator . wake-up after the system enters the sleep or idle mode, it can be woken up from one of various sources listed as follows: an external reset an external falling edge on port a a system interrupt a wdt overfow if the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a wdt overfow, a watchdog timer reset will be initiated. although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the to and pdf flags. the pdf flag is cleared by a system power-up or executing the clear watchdog timer instructions and is set when executing the "halt instruction. the to fag is set if a wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the other fags remain in their original status. each pin on port a can be setup using the pawu register to permit a negative transition on the pin to wake-up the system. when a port a pin wake-up occurs, the program will resume execution at the instruction following the "halt" instruction. rev. 1.50 204 march 06 , 2012 rev. 1.50 205 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro if the system is woken up by an interrupt, then two possible situations may occur. the frst is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "halt instruction. in this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. the other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. if an interrupt request fag is set high before entering the sleep or idle mode, the wake-up function of the related interrupt will be disabled. low voltage detector C lvd each device has a low voltage detector function, also known as lvd. this enabled the device to monitor the power supply voltage, v dd , and provide a warning signal should it fall below a certain level. this function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. the low voltage detector also has the capability of generating an interrupt signal. lvd register the low voltage detector function is controlled using a single register with the name lvdc. three bits in this register, vlvd2~vlvd0, are used to select one of eight fxed voltages below which a low voltage condition will be detemined. a low voltage condition is indicated when the lvdo bit is set. if the lvdo bit is low, this indicates that the v dd voltage is above the preset low voltage value. the lvden bit is used to control the overall on/off function of the low voltage detector. setting the bit high will enable the low voltage detector. clearing the bit to zero will switch off the internal low voltage detector circuits. as the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. lvdc register bit 7 6 5 4 3 2 1 0 name lvdo lvden vlvd2 vlvd1 vlvd0 r/w r r/w r/w r/w r/w por 0 0 0 0 0 bit 7~6 unimplemented, read as "0" bit 5 lvdo : lvd output flag 0: no low voltage detect 1: low voltage detect bit lvden : low voltage detector control 0: disable 1: enable bit 3 unimplemented, read as "0" bit 2~0 vlvd2 ~ vlvd0 : select lvd voltage 000: 2.0v 001: 2.2v 010: 2.4v 011: 2.7v 100: 3.0v 101: 3.3v 110: 3.6v 111: 4.4v ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 204 march 06 , 2012 rev. 1.50 205 march 06 , 2012 lvd operation the low voltage detector function operates by comparing the power supply voltage, v dd , with a pre-specifed voltage level stored in the lvdc register. this has a range of between 2.0v and 4.4v. when the power supply voltage, v dd , falls below this pre-determined value, the lvdo bit will be set high indicating a low power supply voltage condition. the low voltage detector function is supplied by a reference voltage which will be automatically enabled. when the device is powered down the low voltage detector will remain active if the lvden bit is high. after enabling the low voltage detector, a time delay t lvds should be allowed for the circuitry to stabilise before reading the lvdo bit. note also that as the v dd voltage may rise and fall rather slowly, at the voltage nears that of v lvd , there may be multiple bit lvdo transitions. lvd operation the low voltage detector also has its own interrupt which is contained within one of the multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the lvdo bit. the interrupt will only be generated after a delay of t lvd after the lvdo bit has been set high by a low voltage condition. when the device is powered down the low voltage detector will remain active if the lvden bit is high. in this case, the lvf interrupt request fag will be set, causing an interrupt to be generated if v dd falls below the preset lvd voltage. this will cause the device to wake-up from the sleep or idle mode, however if the low voltage detector wake up function is not required then the lvf fag should be frst set high before the device enters the sleep or idle mode. when lvd function is enabled, it is recommenced to clear lvd fag frst, and then enables interrupt function to avoid mistake action. lcd driver for large volume applications, which incorporate an lcd in their design, the use of a custom display rather than a more expensive character based display reduces costs signifcantly. however, the corresponding com and seg signals required, which vary in both amplitude and time, to drive such a custom display require many special considerations for proper lcd operation to occur. these devices all contain an lcd driver function, which with their internal lcd signal generating circuitry and various options, will automatically generate these time and amplitude varying signals to provide a means of direct driving and easy interfacing to a range of custom lcds. all devices include a wide range of options to enable lcd displays of various types to be driven. the table shows the range of options available across the device range. rev. 1.50 206 march 06 , 2012 rev. 1.50 207 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro part no. duty driver no. bias bias type wave type ht67f30 1/2 21x2 1/2 or 1/3 c or r a or b 1/3 21x3 1/4 20x4 ht67f40 1/2 33x2 1/2 or 1/3 c or r a or b 1/3 33x3 1/4 32x4 ht67f40 1/2 41x2 1/2 or 1/3 c or r a or b 1/3 41x3 1/4 40x4 ht67f60 1/2 57x2 1/2 or 1/3 c or r a or b 1/3 57x3 1/4 56x4 lcd selections ? ? ? ? ? ? - ? - c type bias voltage levels r type bias voltage levels ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 206 march 06 , 2012 rev. 1.50 207 march 06 , 2012 lcd memory an area of data memory is especially reserved for use for the lcd display data. this data area is known as the lcd memory. any data written here will be automatically read by the internal display driver circuits, which will in turn automatically generate the necessary lcd driving signals. therefore any data written into this memory will be immediately refected into the actual display connected to the microcontroller. as the lcd memory addresses overlap those of the general purpose data memory, it s stored in its own independent bank 1 area. the data memory bank to be used is chosen by using the bank pointer, which is a special function register in the data memory, with the name, bp. to access the lcd memory therefore requires frst that bank 1 is selected by writing a value of 01h to the bp register. after this, the memory can then be accessed by using indirect addressing through the use of memory pointer mp1. with bank 1 selected, then using mp1 to read or write to the memory area, starting with address 80h, will result in operations to the lcd memory. directly addressing the display memory is not applicable and will result in a data access to the bank 0 general purpose data memory. the accompanying lcd memory map diagrams shows how the internal lcd memory is mapped to the segments and commons of the display for the devices. lcd memory maps for devices with smaller memory capacities can be extrapolated from these diagrams. ? ? ? ht67f30 lcd memory map rev. 1.50 208 march 06 , 2012 rev. 1.50 209 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro ?? ? ? ? ? ht67f40 lcd memory map ?? ? ? HT67F50 lcd memory map ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 208 march 06 , 2012 rev. 1.50 209 march 06 , 2012 ht67f60 lcd memory map ? ? ? lcd registers control registers in the data memory, are used to control the various setup features of the lcd driver. there is one control register for the lcd function, lcdctrl. various bits in this registers control functions such as duty type, bias type, bias resistor selection as well as overall lcd enable and disable. the lcden bit in the lcdctrl register, which provides the overall lcd enable/disable function, will only be effective when the device is in the normal, slow or idle mode. if the device is in the sleep mode then the display will always be disabled. bits rsel0 and rsel1 in the lcdctrl register select the internal bias resistors to supply the lcd panel with the correct bias voltages. a choice to best match the lcd panel used in the application can be selected also to minimise bias current. the type bit in the same register is used to select whether type a or type b lcd control signals are used. three registers, lcdout0, lcdout1, lcdout2 and lcdout3 are used to determine if the output function of display pins seg0~seg31 are used as segment drivers or i/o function s . rev. 1.50 210 march 06 , 2012 rev. 1.50 211 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro lcd reset function the lcd has an internal reset function that is an or function of the inverted lcden bit in the lcdctrl register and the sleep function. the lcd reset signal is active high. the lcdenb signal is the inverse of the lcden bit in the lcdctrl register. reset lcd = (sleep mode and lcden) or lcdenb. lcden sleep mode reset lcd 0 off 0 on 1 off x 1 on lcd reset function clock source the lcd clock source is the internal clock signal, f sub , divided by 8, using an internal divider circuit. the f sub internal clock is supplied by either the lirc or lxt oscillator, the choice of which is determined by a confguration option. for proper lcd operation, this arrangement is provided to generate an ideal lcd clock source frequency of 4khz. f sub clock source lcd clock frequency lirc 4khz lxt 4khz lcd clock source lcd driver output the number of com and seg outputs supplied by the lcd driver, as well as its biasing and duty selections, are dependent upon how the lcd control bits are programmed. the bias type, whether c or r type is selected via a confguration option. the nature of liquid crystal displays require that only ac voltages can be applied to their pixels as the application of dc voltages to lcd pixels may cause permanent damage. for this reason the relative contrast of an lcd display is controlled by the actual rms voltage applied to each pixel, which is equal to the rms value of the voltage on the com pin minus the voltage applied to the seg pin. this differential rms voltage must be greater than the lcd saturation voltage for the pixel to be on and less than the threshold voltage for the pixel to be off. the requirement to limit the dc voltage to zero and to control as many pixels as possible with a minimum number of connections, requires that both a time and amplitude signal is generated and applied to the application lcd. these time and amplitude varying signals are automatically generated by the lcd driver circuits in the microcontroller. what is known as the duty determines the number of common lines used, which are also known as backplanes or coms. the duty, which is chosen by a control bit to have a value of 1/2, 1/3, 1/4 etc and which equates to a com number of 2, 3, 4 etc, therefore defnes the number of time divisions within each lcd signal frame. two types of signal generation are also provided, known as type a and type b, the required type is selected via the type bit in the lcdctrl register. type b offers lower frequency signals, however lower frequencies may introduce fickering and infuence display clarity . ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 210 march 06 , 2012 rev. 1.50 211 march 06 , 2012 lcdctrl register bit 7 6 5 4 3 2 1 0 name type dtyc1 dtyc0 bias rsel1 rsel0 lcden r/w r/w r/w r/w r/w r/w r/w r/w por 0 0 0 0 0 0 0 bit 7 type: lcd type control 0: type a 1: type b bit 6~bit 5 dtyc1, dtyc0 : lcd duty control 00: 1/2 duty 01: 1/3 duty 10: 1/4 duty 11: undefned bit 4 uniplemented, read as 0 bit 3 bias : lcd bias control 0: 1/2 bias 1: 1/3 bias bit 2~bit 1 rsel1, rsel0 : lcd bias resistor select rsel1 rsel0 1/3 bias 1/2 bias 0 0 600k 400k 0 1 300k 200k 1 0 100k 67k 1 1 50k 34k bit 0 lcden : lcd enable control 0: disable 1: enable in the normal, slow or idle mode, the lcd on/off function can be controlled by this bit. in the sleep mode, the lcd is always off. lcdout 0 register bit 7 6 5 4 3 2 1 0 name lcdo7 lcdo6 lcdo5 lcdo4 lcdo3 lcdo2 lcdo1 lcdo0 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ~bit0 lcdo7 ~lcdo0 : seg 7~seg0 output or i/o 0: lcd segment output 1: i/o lcdout 1 register bit 7 6 5 4 3 2 1 0 name lcdo15 lcdo14 lcdo13 lcdo12 lcdo11 lcdo10 lcdo9 lcdo8 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ~bit0 lcd 15~lcdo8 : seg 15~seg8 output or i/o 0: lcd segment output 1: i/o rev. 1.50 212 march 06 , 2012 rev. 1.50 213 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro lcdout 2 register bit 7 6 5 4 3 2 1 0 name lcdo23 lcdo22 lcdo21 lcdo20 lcdo19 lcdo18 lcdo17 lcdo16 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ~bit0 lcd 23~lcd16 : seg 23~seg16 output or i/o 0: lcd segment output 1: i/o lcdout 3 register bit 7 6 5 4 3 2 1 0 name lcdo31 lcdo30 lcdo29 lcdo28 lcdo27 lcdo26 lcdo25 lcdo24 r/w r/w r/w r/w r/w r/w r/w r/w r/w por 1 1 1 1 1 1 1 1 bit 7 ~bit0 lcd 31~lcd24 : seg 31~seg24 output or i/o 0: lcd segment output 1: i/o lcd voltage source and biasing the time and amplitude varying signals generated by the lcd driver function require the generation of several voltage levels for their operation. the number of voltage levels used by the signal depends upon the value of the bias bit in the lcdctrl register. the device can have either r type or c type biasing selected via a confguration option. selecting the c type biasing will enable an internal charge pump whose multiplier ratio can be selected using an additional confguration option. for r type biasing an external lcd voltage source must be supplied on pin vlcd to generate the internal biasing voltages. this could be the microcontroller power supply or some other voltage source. for the r type 1/2 bias selection, three voltage levels vss, va and vb are utilised. the voltage va is equal to the externally supplied voltage source applied to pin vlcd. vb is generated internally by the microcontroller and will have a value equal to vlcd/2. for the r type 1/3 bias selection, four voltage levels vss, va, vb and vc are utilised. the voltage va is equal to vlcd, vb is equal to vlcdx 2/3 while vc is equal to vlcdx1/3. in addition to selecting 1/2 or 1/3 bias, several values of bias resistor can be chosen using bits in the lcdctrl register. different values of internal bias resistors can be selected using the rsel0 and resel1 bits in the lcdctrl register. this along with the voltage on pin vlcd will determine the bias current. the connection to the vmax pin depends upon the voltage that is applied to vlcd. if the vdd voltage is greater than the voltage applied to the vlcd pin then the vmax pin should be connected to vdd, otherwise the vmax pin should be connected to pin vlcd. note that no external capacitors or resistors are required to be connected if r type biasing is used. condition vmax connection vdd > vlcd1 connect vmax to vdd otherwise connect vmax to vlcd r type bias current vmax connection for c type biasing an external lcd voltage source must also be supplied on pin vlcd to generate the internal biasing voltages. the c type biasing scheme uses an internal charge pump circuit, which in the case of the 1/3 bias selection can generate voltages higher than what is supplied on vlcd. this feature is useful in applications where the microcontroller supply voltage is less than the supply voltage required by the lcd. an additional charge pump capacitor must also be connected between pins c1 and c2 to generate the necessary voltage levels. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 212 march 06 , 2012 rev. 1.50 213 march 06 , 2012 for the c type 1/2 bias selection, three voltage levels vss, va and vb are utilised. the voltage va is generated internally and has a value of vlcd. vb will have a value equal to vax0.5. for the c type 1/2 bias confguration vc is not used. for the c type 1/3 bias selection, four voltage levels vss, va, vb and vc are utilised. the voltage va is generated internally and has a value of vlcdx1.5. vb will have a value equal to vax 2/3 and vc will have a value equal to va x 1/3. the connection to the vmax pin depends upon the bias and the voltage that is applied to vlcd, the details are shown in the table. it is extremely important to ensure that these charge pump generated internal voltages do not exceed the maximum vdd voltage of 5.5v. biasing type vmax connection 1/3 bias vdd>vlcdx1.5 connect vmax to vdd otherwise connect vmax to v1 1/2 bias vdd>vlcd connect vmax to vdd otherwise connect vmax to vlcd c type biasing vmax connection lcd waveform timing diagrams the accompanying timing diagrams depict the display driver signals generated by the microcontroller for various values of duty and bias. the huge range of various permutations only permit a few types to be displayed here. lcd driver output C type a - 1/2 duty, 1/2 bias note: for 1/2 bias, va=vlcd, vb=vlcdx1/2 for both r and c type. rev. 1.50 214 march 06 , 2012 rev. 1.50 215 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro lcd driver output C type a- 1/3 duty, 1/2 bias note: for 1/2 bias, the va=vlcd, vb=vlcdx1/2 for both r and c type. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 214 march 06 , 2012 rev. 1.50 215 march 06 , 2012 ? ?? lcd driver output C type a - 1/4 duty, 1/3 bias note: for 1/3 r type bias, the va=vlcd, vb=vlcdx2/3 and vc=vlcdx1/3. for 1/3 c type bias, the va=vlcdx1.5, vb=vlcd and vc=vlcdx1/2. rev. 1.50 216 march 06 , 2012 rev. 1.50 217 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro lcd driver output C type a- 1/3 duty, 1/3 bias note: for 1/3 r type bias, the va=vlcd, vb=vlcd2/3 and vc=vlcd1/3. for 1/3 c type bias, va=vlcd1.5, vb=vlcd and vc=vlcd1/2. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 216 march 06 , 2012 rev. 1.50 217 march 06 , 2012 lcd driver output C type b- 1/2 duty, 1/2 bias note: for 1/2 bias, the va=vlcd, vb=vlcdx1/2 for both r and c type. rev. 1.50 218 march 06 , 2012 rev. 1.50 219 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro 1 frame com0 com1 com2 all segments are off com0 side segments are on com1 side segments are on com2 side segments are on (other combinations are omitted) com0, 1 side segments are on normal operation mode during reset or lcd off com0, com1, com2 all segment outputs com0, 2 side segments are on va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss all segments are on lcd driver output C type b- 1/3 duty, 1/3 bias note: for 1/3 r type bias, the va=vlcd, vb=vlcd2/3 and vc=vlcd1/3. for 1/3 c type bias, va=vlcd1.5, vb=vlcd and vc=vlcd1/2. ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 218 march 06 , 2012 rev. 1.50 219 march 06 , 2012 va vb vc vss 1 frame va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss va vb vc vss com0 com1 com2 all segments are off com0 side segments are on com3 com1 side segments are on com2 side segments are on (other combinations are omitted) com0, 1 side segments are on com3 side segments are on normal operation mode during reset or lcd off com0, com1, com2, com3 all segment outputs va vb vc vss va vb vc vss va vb vc vss com0, 2 side segments are on va vb vc vss com0, 3 side segments are on va vb vc vss all segments are on lcd driver output C type b- 1/4 duty, 1/3 bias note: for 1/3 r type bias, the va=vlcd, vb=vlcd2/3 and vc=vlcd1/3. for 1/3 c type bias, va=vlcd1.5, vb=vlcd and vc=vlcd1/2. rev. 1.50 220 march 06 , 2012 rev. 1.50 221 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro programming considerations certain precautions must be taken when programming the lcd. one of these is to ensure that the lcd memory is properly initialised after the microcontroller is powered on. like the general purpose data memory, the contents of the lcd memory are in an unknown condition after power- on. as the contents of the lcd memory will be mapped into the actual display, it is important to initialise this memory area into a known condition soon after applying power to obtain a proper display pattern. consideration must also be given to the capacitive load of the actual lcd used in the application. as the load presented to the microcontroller by lcd pixels can be generally modeled as mainly capacitive in nature, it is important that this is not excessive, a point that is particularly true in the case of the com lines which may be connected to many lcd pixels. the accompanying diagram depicts the equivalent circuit of the lcd. one additional consideration that must be taken into account is what happens when the microcontroller enters the idle or slow mode. the lcden control bit in the lcdctrl register permits the display to be powered off to reduce power consumption. if this bit is zero, the driving signals to the display will cease, producing a blank display pattern but reducing any power consumption associated with the lcd. after power-on, note that as the lcden bit will be cleared to zero, the display function will be disabled. lcd panel equivalent circuit ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 220 march 06 , 2012 rev. 1.50 221 march 06 , 2012 confguration options confguration options refer to certain options within the mcu that are programmed into the device during the programming process. during the development process, these options are selected using the ht-ide software development tools. as these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. all options must be defned for proper system function, the details of which are shown in the table. no. options oscillator options 1 high speed system oscillator selection - f h : 1. hxt 2. erc 3. hirc 4. ec 2 low speed system oscillator selection - f l : 1. lxt 2. lirc 3 hxt mode 1. 1mhz~12mhz 2. 455khz 4 wdt clock selection - f s : 1. f su b 2. f sys /4 5 hirc frequency selection: 1. 4mhz 2. 8mhz 3. 12mhz note: the f sub and the f tbc clock source are lxt or lirc selection by the f l frqjxudwlrqrswlrq reset pin options 6 pb0/res pin options: 1. res pin 2. i/o pin watchdog options 7 watchdog timer function: 1. enable 2. disable 8 clrwdt instructions selection: 1. 1 instructions 2. 2 instructions lvr options 9 lvr function: 1. enable 2. disable 10 lvr voltage selection: 1. 2.10v 2. 2.55v 3. 3.15v 4. 4.20v sim options 11 sim function: 1. enable 2. disable 12 spi - wcol bit: 1. enable 2. disable rev. 1.50 222 march 06 , 2012 rev. 1.50 223 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro no. options 13 spi - csen bit: 1. enable 2. disable 14 i 2 c debounce time selection: 1. no debounce 2. 1 system clock debounce 3. 2 system clock debounce spia options 15 spia function: 1. enable 2. disable 16 spia - sawcol bit: 1. enable 2. disable 17 spia - sacsen bit: 1. enable 2. disable tmr/int options 18 tmr/int pin input flter function: 1. enable 2. disable lcd options 19 lcd r type or c type selection: 1. r type 2. c type 20 lcd voltage 1. vlcd is 3.0v or 4.5v 2. vlcd is 1.5v ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 222 march 06 , 2012 rev. 1.50 223 march 06 , 2012 application circuits ? ? ? ? ? ? ? ? ? ? ? ? - ? ? - ? ? ? ? ?? ? ???? note: "*": it is recommended that this component is added for added esd protection. "**": it is recommended that this component is added in environments where power line noise is signifcant. rev. 1.50 224 march 06 , 2012 rev. 1.50 225 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and fexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. for easier understanding of the various instruction codes, they have been subdivided into several functional groupings. instruction timing most instructions are implemented within one instruction cycle. the exceptions to this are branch, call, or table read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5s and branch or call instructions would be implemented within 1s. although instructions which require one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instructions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to implement. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instructions would be "clr pcl" or "mov pcl, a". for the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specifc immediate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specifed. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 224 march 06 , 2012 rev. 1.50 225 march 06 , 2012 rotate instructions exist depending on program requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specifed locations using the jmp instruction or to a subroutine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made regarding the condition of a certain data memory or individual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. bit operations the ability to provide single bit operations on data memory is an extremely fexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "set [m].i" or "clr [m]. i" instructions respectively. the feature removes the need for programmers to frst read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write process is taken care of automatically when these bit operation instructions are used. table read operations data storage is normally implemented by using registers. however, when working with large amounts of fxed data, the volume involved often makes it inconvenient to store the fxed data in the data memory. to overcome this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the "halt" instruction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electromagnetic environments. for their relevant operations, refer to the functional related sections. rev. 1.50 226 march 06 , 2012 rev. 1.50 227 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. table conventions x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] add data memory to acc 1 z, c, ac, ov addm a,[m] add acc to data memory 1 note z, c, ac, ov add a,x add immediate data to acc 1 z, c, ac, ov adc a,[m] add data memory to acc with carry 1 z, c, ac, ov adcm a,[m] add acc to data memory with carry 1 note z, c, ac, ov sub a,x subtract immediate data from the acc 1 z, c, ac, ov sub a,[m] subtract data memory from acc 1 z, c, ac, ov subm a,[m] subtract data memory from acc with result in data memory 1 note z, c, ac, ov sbc a,[m] subtract data memory from acc with carry 1 z, c, ac, ov sbcm a,[m] subtract data memory from acc with carry, result in data memory 1 note z, c, ac, ov daa [m] decimal adjust acc for addition with result in data memory 1 note c logic operation and a,[m] logical and data memory to acc 1 z or a,[m] logical or data memory to acc 1 z xor a,[m] logical xor data memory to acc 1 z andm a,[m] logical and acc to data memory 1 note z orm a,[m] logical or acc to data memory 1 note z xorm a,[m] logical xor acc to data memory 1 note z and a,x logical and immediate data to acc 1 z or a,x logical or immediate data to acc 1 z xor a,x logical xor immediate data to acc 1 z cpl [m] complement data memory 1 note z cpla [m] complement data memory with result in acc 1 z increment & decrement inca [m] increment data memory with result in acc 1 z inc [m] increment data memory 1 note z deca [m] decrement data memory with result in acc 1 z dec [m] decrement data memory 1 note z rotate rra [m] rotate data memory right with result in acc 1 none rr [m] rotate data memory right 1 note none rrca [m] rotate data memory right through carry with result in acc 1 c rrc [m] rotate data memory right through carry 1 note c rla [m] rotate data memory left with result in acc 1 none rl [m] rotate data memory left 1 note none rlca [m] rotate data memory left through carry with result in acc 1 c rlc [m] rotate data memory left through carry 1 note c ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 226 march 06 , 2012 rev. 1.50 227 march 06 , 2012 mnemonic description cycles flag affected data move mov a,[m] move data memory to acc 1 none mov [m],a move acc to data memory 1 note none mov a,x move immediate data to acc 1 none bit operation clr [m].i clear bit of data memory 1 note none set [m].i set bit of data memory 1 note none branch jmp addr jump unconditionally 2 none sz [m] skip if data memory is zero 1 note none sza [m] skip if data memory is zero with data movement to acc 1 note none sz [m].i skip if bit i of data memory is zero 1 note none snz [m].i skip if bit i of data memory is not zero 1 note none siz [m] skip if increment data memory is zero 1 note none sdz [m] skip if decrement data memory is zero 1 note none siza [m] skip if increment data memory is zero with result in acc 1 note none sdza [m] skip if decrement data memory is zero with result in acc 1 note none call addr subroutine call 2 none ret return from subroutine 2 none ret a,x return from subroutine and load immediate data to acc 2 none reti return from interrupt 2 none table read tabrdc [m] read table (current page) to tblh and data memory 2 note none tabrdl [m] read table (last page) to tblh and data memory 2 note none miscellaneous nop no operation 1 none clr [m] clear data memory 1 note none set [m] set data memory 1 note none clr wdt clear watchdog timer 1 to, pdf clr wdt1 pre-clear watchdog timer 1 to, pdf clr wdt2 pre-clear watchdog timer 1 to, pdf swap [m] swap nibbles of data memory 1 note none swapa [m] swap nibbles of data memory with result in acc 1 none halt enter power down mode 1 to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the "clr wdt1" and "clr wdt2" instructions the to and pdf fags may be affected by the execution status. the to and pdf flags are cleared after both "clr wdt1" and "clr wdt2" instructions are consecutively executed. otherwise the to and pdf flags remain unchanged. rev. 1.50 228 march 06 , 2012 rev. 1.50 229 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro instruction defnition add data memory to acc with carry the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the accumulator. acc acc + [m] + c ov, z, ac, c add acc to data memory with carry the contents of the specifed data memory, accumulator and the carry fag are added. the result is stored in the specifed data memory. [m] acc + [m] + c ov, z, ac, c add data memory to acc the contents of the specifed data memory and the accumulator are added. the result is stored in the accumulator. acc acc + [m] ov, z, ac, c add immediate data to acc the contents of the accumulator and the specifed immediate data are added. the result is stored in the accumulator. ac acc + x ov, z, ac, c add acc to data memory the contents of the specifed data memory and the accumulator are added. the result is stored in the specifed data memory. [m] acc + [m] ov, z, ac, c logical and data memory to acc data in the accumulator and the specifed data memory perform a bitwise logical and operation. the result is stored in the accumulator. acc acc " and " [m] z logical and immediate data to acc data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. acc acc " and " x z logical and acc to data memory data in the specifed data memory and the accumulator perform a bitwise logical and operation. the result is stored in the data memory. [m] acc " and " [m] z adc a,[m] description operation affected fag(s) adcm a,[m] description operation affected fag(s) add a,[m] description operation affected fag(s) add a,x description operation affected fag(s) addm a,[m] description operation affected fag(s) and a,[m] description operation affected fag(s) and a,x description operation affected fag(s) andm a,[m] description operation affected fag(s) ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 228 march 06 , 2012 rev. 1.50 229 march 06 , 2012 subroutine call unconditionally calls a subroutine at the specifed address. the program counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruction. stack program counter + 1 program counter addr none clear data memory each bit of the specifed data memory is cleared to 0. [m] 00h none clear bit of data memory bit i of the specifed data memory is cleared to 0. [m].i 0 none clear watchdog timer the to, pdf fags and the wdt are all cleared. wdt cleared to 0 pdf 0 to, pdf pre-clear watchdog timer the to, pdf fags and the wdtare all cleared. note that this instruction works in conjunction with clr wdt2 and must be executed alternately with clr wdt2 to have effect. repetitively executing this instruction without alternately executing clr wdt2 will have no effect. wdt cleared to 0 pdf 0 to, pdf pre-clear watchdog timer the to, pdf fags and the wdtare all cleared. note that this instruction works in conjunction with clr wdt1 and must be executed alternately with clr wdt1 to have effect. repetitively executing this instruction without alternately executing wdt cleared to 0 pdf 0 to, pdf call addr description operation affected fag(s) clr [m] description operation affected fag(s) clr [m].i description operation affected fag(s) clr wdt description operation affected fag(s) clr wdt1 description operation affected fag(s) clr wdt2 description operation affected fag(s) rev. 1.50 230 march 06 , 2012 rev. 1.50 231 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro complement data memory each bit of the specified data memory is logically complemented (1 ' s complement). bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] z complement data memory with result in acc each bit of the specified data memory is logically complemented (1 ' s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. acc [m] z decimal-adjust acc for addition with result in data memory convert the contents of the accumulator value to a bcd ( binary coded decimal) value resulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac fag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c fag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by adding 00h, 06h, 60h or 66h depending on the accumulator and fag conditions. only the c fag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h c decrement data memory data in the specifed data memory is decremented by 1. [m] [m] ? 1 z decrement data memory with result in acc data in the specifed data memory is decremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. acc [m] ? 1 z cpl [m] description operation affected fag(s) cpla [m] description operation affected fag(s) daa [m] description operation affected fag(s) dec [m] description operation affected fag(s) deca [m] description operation affected fag(s) ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 230 march 06 , 2012 rev. 1.50 231 march 06 , 2012 enter power down mode this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. to 0 pdf 0 to, pdf increment data memory data in the specifed data memory is incremented by 1. [m] [m]+1 z increment data memory with result in acc data in the specifed data memory is incremented by 1. the result is stored in the accumulator. the contents of the data memory remain unchanged. acc [m]+1 z jump unconditionally the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. program counter addr none move data memory to acc the contents of the specifed data memory are copied to the accumulator. acc [m] none move immediate data to acc the immediate data specifed is loaded into the accumulator. acc x none move acc to data memory the contents of the accumulator are copied to the specifed data memory. [m] acc none no operation no operation is performed. execution continues with the next instruction. no operation none halt description operation affected fag(s) inc [m] description operation affected fag(s) inca [m] description operation affected fag(s) jmp addr description operation affected fag(s) mov a,[m] description operation affected fag(s) mov a,x description operation affected fag(s) mov [m],a description operation affected fag(s) nop description operation affected fag(s) rev. 1.50 232 march 06 , 2012 rev. 1.50 233 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro logical or data memory to acc data in the accumulator and the specifed data memory perform a bitwise logical or operation. the result is stored in the accumulator. acc acc " or " [m] z logical or immediate data to acc data in the accumulator and the specified immediate data perform a bitwise logical or operation. the result is stored in the accumulator. acc acc " or " x z logical or acc to data memory data in the specifed data memory and the accumulator perform a bitwise logical or operation. the result is stored in the data memory. [m] acc " or " [m] z return from subroutine the program counter is restored from the stack. program execution continues at the restored address. program counter stack none return from subroutine and load immediate data to acc the program counter is restored from the stack and the accumulator loaded with the specifed immediate data. program execution continues at the restored address. program counter stack acc x none return from interrupt the program counter is restored from the stack and the interrupts are re-enabled by setting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed before returning to the main program. program counter stack emi 1 none rotate data memory left the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 none or a,[m] description operation affected fag(s) or a,x description operation affected fag(s) orm a,[m] description operation affected fag(s) ret description operation affected fag(s) ret a,x description operation affected fag(s) reti description operation affected fag(s) rl [m] description operation affected fag(s) ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 232 march 06 , 2012 rev. 1.50 233 march 06 , 2012 rotate data memory left with result in acc the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 none rotate data memory left through carry the contents of the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 c rotate data memory left through carry with result in acc data in the specifed data memory and the carry fag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry fag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 c rotate data memory right the contents of the specifed data memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 none rotate data memory right with result in acc data in the specifed data memory and the carry fag are rotated right by 1 bit with bit 0 rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 none rotate data memory right through carry the contents of the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 c rla [m] description operation affected fag(s) rlc [m] description operation affected fag(s) rlca [m] description operation affected fag(s) rr [m] description operation affected fag(s) rra [m] description operation affected fag(s) rrc [m] description operation affected fag(s) rev. 1.50 234 march 06 , 2012 rev. 1.50 235 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro rotate data memory right through carry with result in acc data in the specifed data memory and the carry fag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry fag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 c subtract data memory from acc with carry the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. acc acc ? [m] ? c ov, z, ac, c subtract data memory from acc with carry and result in data memory the contents of the specifed data memory and the complement of the carry fag are subtracted from the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. acc acc ? [m] ? c ov, z, ac, c skip if decrement data memory is 0 the contents of the specifed data memory are frst decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. [m] [m] ? 1 skip if [m] = 0 none skip if decrement data memory is zero with result in acc the contents of the specifed data memory are frst decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. acc [m] ? 1 skip if acc = 0 none rrca [m] description operation affected fag(s) sbc a,[m] description operation affected fag(s) sbcm a,[m] description operation affected fag(s) sdz [m] description operation affected fag(s) sdza [m] description operation affected fag(s) ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 234 march 06 , 2012 rev. 1.50 235 march 06 , 2012 set data memory each bit of the specifed data memory is set to 1. [m] ffh none set bit of data memory bit i of the specifed data memory is set to 1. [m].1 1 none skip if increment data memory is 0 the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 skip if [m] = 0 none skip if increment data memory is zero with result in acc the contents of the specifed data memory are frst incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specifed data memory contents remain unchanged. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. acc [m] + 1 skip if acc = 0 none skip if bit i of data memory is not 0 if bit i of the specifed data memory is not 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. skip if [m].i 0 none subtract data memory from acc the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. acc acc ? [m] ov, z, ac, c set [m] description operation affected fag(s) set [m].i description operation affected fag(s) siz [m] description operation affected fag(s) siza [m] description operation affected fag(s) snz [m].i description operation affected fag(s) sub a,[m] description operation affected fag(s) rev. 1.50 236 march 06 , 2012 rev. 1.50 237 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro subtract data memory from acc with result in data memory the specifed data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. [m] acc ? [m] ov, z, ac, c subtract immediate data from acc the immediate data specifed by the code is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c fag will be cleared to 0, otherwise if the result is positive or zero, the c fag will be set to 1. acc acc ? x ov, z, ac, c swap nibbles of data memory the low-order and high-order nibbles of the specified data memory are interchanged. [m].3~[m].0?[m].7 ~ [m].4 none swap nibbles of data memory with result in acc the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 none skip if data memory is 0 if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. skip if [m] = 0 none skip if data memory is 0 with data movement to acc the contents of the specifed data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. acc [m] skip if [m] = 0 none subm a,[m] description operation affected fag(s) sub a,x description operation affected fag(s) swap [m] description operation affected fag(s) swapa [m] description operation affected fag(s) sz [m] description operation affected fag(s) sza [m] description operation affected fag(s) ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 236 march 06 , 2012 rev. 1.50 237 march 06 , 2012 skip if bit i of data memory is 0 if bit i of the specifed data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. skip if [m].i = 0 none read table (current page) to tblh and data memory the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. [m] program code (low byte) tblh program code (high byte) none read table (last page) to tblh and data memory the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specifed data memory and the high byte moved to tblh. [m] program code (low byte) tblh program code (high byte) none logical xor data memory to acc data in the accumulator and the specifed data memory perform a bitwise logical xor operation. the result is stored in the accumulator. acc acc " xor " [m] z logical xor acc to data memory data in the specifed data memory and the accumulator perform a bitwise logical xor operation. the result is stored in the data memory. [m] acc " xor " [m] z logical xor immediate data to acc data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. acc acc " xor " x z sz [m].i description operation affected fag(s) tabrdc [m] description operation affected fag(s) tabrdl [m] description operation affected fag(s) xor a,[m] description operation affected fag(s) xorm a,[m] description operation affected fag(s) xor a,x description operation affected fag(s) rev. 1.50 238 march 06 , 2012 rev. 1.50 239 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro package information note that the package information provided here is for consultation purposes only. as this information may be updated at regular intervals users are reminded to consult the holtek website (http://www.holtek.com.tw/english/ literature/package.pdf) for the latest version of the package information. 48-pin lqfp (7mmx7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 D 0.358 b 0.272 D 0.280 c 0.350 D 0.358 d 0.272 D 0.280 e D 0.020 D f D 0.008 D g 0.053 D 0.057 h D D 0.063 i D 0.004 D j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.50 D f D 0.20 D g 1.35 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.20 0 D 7 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 238 march 06 , 2012 rev. 1.50 239 march 06 , 2012 64-pin lqfp (7mmx7mm) outline dimensions lqfp outline dimensions 64-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.016 f 0.005 0.009 g 0.053 0.057 h 0.063 i 0.002 0.006 j 0.018 0.030 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.40 f 0.13 0.23 g 1.35 1.45 h 1.60 i 0.05 0.15 j 0.45 0.75 k 0.09 0.20 0 7 package information 1 february 8, 2010 symbol dimensions in inch min. nom. max. a 0.350 D 0.358 b 0.272 D 0.280 c 0.350 D 0.358 d 0.272 D 0.280 e D 0.016 D f 0.005 D 0.009 g 0.053 D 0.057 h D D 0.063 i 0.002 D 0.006 j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 8.90 D 9.10 b 6.90 D 7.10 c 8.90 D 9.10 d 6.90 D 7.10 e D 0.40 D f 0.13 D 0.23 g 1.35 D 1.45 h D D 1.60 i 0.05 D 0.15 j 0.45 D 0.75 k 0.09 D 0.20 0 D 7 rev. 1.50 240 march 06 , 2012 rev. 1.50 241 march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro 80-pin lqfp (10mmx10mm) outline dimensions lqfp outline dimensions 80-pin lqfp (10mm 10mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.469 0.476 b 0.390 0.398 c 0.469 0.476 d 0.390 0.398 e 0.016 f 0.006 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 11.90 12.10 b 9.90 10.10 c 11.90 12.10 d 9.90 10.10 e 0.40 f 0.16 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 0 7 package information 1 april 1, 2010 symbol dimensions in inch min. nom. max. a 0.469 D 0.476 b 0.390 D 0.398 c 0.469 D 0.476 d 0.390 D 0.398 e D 0.016 D f D 0.006 D g 0.053 D 0.057 h D D 0.063 i D 0.004 D j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 11.90 D 12.10 b 9.90 D 10.10 c 11.90 D 12.10 d 9.90 D 10.10 e D 0.40 D f D 0.16 D g 1.35 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.20 0 D 7 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eeprom rev. 1.50 240 march 06 , 2012 rev. 1.50 241 march 06 , 2012 100-pin lqfp (14mmx14mm) outline dimensions 100-pin lqfp (14mm 14mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.626 0.634 b 0.547 0.555 c 0.626 0.634 d 0.547 0.555 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 0 7 symbol dimensions in mm min. nom. max. a 15.90 16.10 b 13.90 14.10 c 15.90 16.10 d 13.90 14.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 0 7 package information 1 april 13, 2011 symbol dimensions in inch min. nom. max. a 0.626 D 0.634 b 0.547 D 0.555 c 0.626 D 0.634 d 0.547 D 0.555 e D 0.020 D f D 0.008 D g 0.053 D 0.057 h D D 0.063 i D 0.004 D j 0.018 D 0.030 k 0.004 D 0.008 0 D 7 symbol dimensions in mm min. nom. max. a 15.90 D 16.10 b 13.90 D 14.10 c 15.90 D 16.10 d 13.90 D 14.10 e D 0.50 D f D 0.20 D g 1.35 D 1.45 h D D 1.60 i D 0.10 D j 0.45 D 0.75 k 0.10 D 0.20 0 D 7 rev. 1.50 242 march 06 , 2012 rev. 1.50 pb march 06 , 2012 ht67f30/ht67f40/HT67F50/ht67f60 tinypower tm a/d flash type 8-bit mcu with lcd & eepro holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales offce) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales offce) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales offce) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com copyright ? 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modifcation, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek's products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notifcation. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw . |
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